diff options
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 56 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/neon.txt | 2 |
2 files changed, 42 insertions, 16 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 725a8a2abd..ad1692ca3b 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2769,8 +2769,11 @@ static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2819,8 +2822,11 @@ static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2876,8 +2882,11 @@ static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2931,8 +2940,11 @@ static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -2989,8 +3001,11 @@ static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -3043,8 +3058,11 @@ static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -3103,8 +3121,11 @@ static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); @@ -3158,8 +3179,11 @@ static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, } CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); - if (Rm != 0xF && Rm != 0xD) { - CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + if (Rm != 0xF) { + if (Rm != 0xD) + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); + else + Inst.addOperand(MCOperand::CreateReg(0)); } CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index b909c4bb4b..6068a38c3d 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -1848,4 +1848,6 @@ 0x0 0xc 0xa0 0xf4 # CHECK: vld1.8 {d0[]}, [r0], r0 +0x0d 0x03 0x80 0xf4 +# CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! |