diff options
28 files changed, 166 insertions, 161 deletions
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp index c9be16f192..d30881f593 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp @@ -220,8 +220,8 @@ void InstructionSelection::InsertCodeForPhis(Function &F) { MachineCodeForInstruction &MCforPN = MachineCodeForInstruction::get (PN); for (unsigned i = 0; i < PN->getNumIncomingValues(); ++i) { std::vector<MachineInstr*> mvec, CpVec; - Target.getRegInfo().cpValue2Value(PN->getIncomingValue(i), PhiCpRes, - mvec); + Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i), + PhiCpRes, mvec); for (std::vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) { std::vector<MachineInstr*> CpVec2 = @@ -235,7 +235,7 @@ void InstructionSelection::InsertCodeForPhis(Function &F) { } // Insert a copy instruction from PhiCpRes to PN. std::vector<MachineInstr*> mvec; - Target.getRegInfo().cpValue2Value(PhiCpRes, const_cast<PHINode*>(PN), + Target.getRegInfo()->cpValue2Value(PhiCpRes, const_cast<PHINode*>(PN), mvec); BB->insert(BB->begin(), mvec.begin(), mvec.end()); MCforPN.insert (MCforPN.end (), mvec.begin (), mvec.end ()); diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp index 90728485b7..e0f43b529b 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp @@ -40,7 +40,7 @@ InsertCodeToLoadConstant(Function *F, MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr); TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue); - target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg, + target.getInstrInfo()->CreateCodeToLoadConst(target, F, opValue, tmpReg, loadConstVec, mcfi); // Record the mapping from the tmp VM instruction to machine instruction. @@ -66,14 +66,14 @@ ChooseRegOrImmed(int64_t intValue, getImmedValue = 0; if (canUseImmed && - target.getInstrInfo().constantFitsInImmedField(opCode, intValue)) { + target.getInstrInfo()->constantFitsInImmedField(opCode, intValue)) { opType = isSigned? MachineOperand::MO_SignExtendedImmed : MachineOperand::MO_UnextendedImmed; getImmedValue = intValue; } else if (intValue == 0 && - target.getRegInfo().getZeroRegNum() != (unsigned)-1) { + target.getRegInfo()->getZeroRegNum() != (unsigned)-1) { opType = MachineOperand::MO_MachineRegister; - getMachineRegNum = target.getRegInfo().getZeroRegNum(); + getMachineRegNum = target.getRegInfo()->getZeroRegNum(); } return opType; @@ -95,7 +95,7 @@ ChooseRegOrImmed(Value* val, // TargetInstrInfo::ConvertConstantToIntType() does the right conversions: bool isValidConstant; uint64_t valueToUse = - target.getInstrInfo().ConvertConstantToIntType(target, val, val->getType(), + target.getInstrInfo()->ConvertConstantToIntType(target, val, val->getType(), isValidConstant); if (! isValidConstant) return MachineOperand::MO_VirtualRegister; @@ -130,7 +130,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr, std::vector<MachineInstr*> MVec; MachineOpCode opCode = minstr->getOpcode(); - const TargetInstrInfo& instrInfo = target.getInstrInfo(); + const TargetInstrInfo& instrInfo = *target.getInstrInfo(); int resultPos = instrInfo.getResultPos(opCode); int immedPos = instrInfo.getImmedConstantPos(opCode); diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp index 9d5492371a..149df1064f 100644 --- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp +++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp @@ -295,12 +295,12 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { // If the current machine instruction has delay slots, mark values // used by this instruction as live before and after each delay slot // instruction (After(MI) is the same as Before(MI+1) except for last MI). - if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(MI->getOpcode())) { + if (unsigned DS = TM.getInstrInfo()->getNumDelaySlots(MI->getOpcode())) { MachineBasicBlock::const_iterator fwdMII = MII.base(); // ptr to *next* MI for (unsigned i = 0; i < DS; ++i, ++fwdMII) { assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?"); const MachineInstr* DelaySlotMI = fwdMII; - if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpcode())) { + if (! TM.getInstrInfo()->isNop(DelaySlotMI->getOpcode())) { set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet); if (i+1 == DS) set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet); diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp index 5f414ec5a3..e6a687741b 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp +++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp @@ -29,7 +29,7 @@ unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); } LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm, std::vector<RegClass *> &RCL) - : Meth(F), TM(tm), RegClassList(RCL), MRI(tm.getRegInfo()) { } + : Meth(F), TM(tm), RegClassList(RCL), MRI(*tm.getRegInfo()) { } LiveRangeInfo::~LiveRangeInfo() { @@ -176,8 +176,8 @@ void LiveRangeInfo::constructLiveRanges() { // If the machine instruction is a call/return instruction, add it to // CallRetInstrList for processing its args, ret value, and ret addr. // - if(TM.getInstrInfo().isReturn(MInst->getOpcode()) || - TM.getInstrInfo().isCall(MInst->getOpcode())) + if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) || + TM.getInstrInfo()->isCall(MInst->getOpcode())) CallRetInstrList.push_back(MInst); // iterate over explicit MI operands and create a new LR @@ -244,9 +244,9 @@ void LiveRangeInfo::suggestRegs4CallRets() { MachineInstr *MInst = *It; MachineOpCode OpCode = MInst->getOpcode(); - if ((TM.getInstrInfo()).isReturn(OpCode)) + if (TM.getInstrInfo()->isReturn(OpCode)) MRI.suggestReg4RetValue(MInst, *this); - else if ((TM.getInstrInfo()).isCall(OpCode)) + else if (TM.getInstrInfo()->isCall(OpCode)) MRI.suggestRegs4CallArgs(MInst, *this); else assert( 0 && "Non call/ret instr in CallRetInstrList" ); diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index b813ee4971..e8d6010ba7 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -240,7 +240,7 @@ void PhyRegAlloc::buildInterferenceGraphs() { // get the LV set after the instruction const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB); - bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode()); + bool isCallInst = TM.getInstrInfo()->isCall(MInst->getOpcode()); if (isCallInst) { // set the isCallInterference flag of each live range which extends @@ -265,7 +265,7 @@ void PhyRegAlloc::buildInterferenceGraphs() { // another. This must be done because pseudo-instructions may be // expanded to multiple instructions by the assembler, so all the // operands must get distinct registers. - if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode())) + if (TM.getInstrInfo()->isPseudoInstr(MInst->getOpcode())) addInterf4PseudoInstr(MInst); // Also add interference for any implicit definitions in a machine @@ -453,7 +453,7 @@ void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII, // Now insert caller-saving code before/after the call. // Do this before inserting spill code since some registers must be // used by save/restore and spill code should not use those registers. - if (TM.getInstrInfo().isCall(Opcode)) { + if (TM.getInstrInfo()->isCall(Opcode)) { AddedInstrns &AI = AddedInstrMap[MInst]; insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst, MBB.getBasicBlock()); @@ -497,7 +497,7 @@ void PhyRegAlloc::updateMachineCode() // their assigned registers or insert spill code, as appropriate. // Also, fix operands of call/return instructions. for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII) - if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode())) + if (! TM.getInstrInfo()->isDummyPhiInstr(MII->getOpcode())) updateInstruction(MII, MBB); // Now, move code out of delay slots of branches and returns if needed. @@ -516,15 +516,15 @@ void PhyRegAlloc::updateMachineCode() // If so, we need to handle spill differently but annulling is not yet used. for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII) if (unsigned delaySlots = - TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) { + TM.getInstrInfo()->getNumDelaySlots(MII->getOpcode())) { MachineBasicBlock::iterator DelaySlotMI = next(MII); assert(DelaySlotMI != MBB.end() && "no instruction for delay slot"); // Check the 2 conditions above: // (1) Does a branch need instructions added after it? // (2) O/w does delay slot instr. need instrns before or after? - bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) || - TM.getInstrInfo().isReturn(MII->getOpcode())); + bool isBranch = (TM.getInstrInfo()->isBranch(MII->getOpcode()) || + TM.getInstrInfo()->isReturn(MII->getOpcode())); bool cond1 = (isBranch && AddedInstrMap.count(MII) && AddedInstrMap[MII].InstrnsAfter.size() > 0); @@ -549,7 +549,7 @@ void PhyRegAlloc::updateMachineCode() // instruction out of the delay slot). On cond2 we need // to insert a nop in place of the moved instruction if (cond2) { - MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1)); + MBB.insert(MII, BuildMI(TM.getInstrInfo()->getNOPOpCode(),1)); } } else { @@ -565,7 +565,7 @@ void PhyRegAlloc::updateMachineCode() MachineInstr *MInst = MII; // do not process Phis - if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode())) + if (TM.getInstrInfo()->isDummyPhiInstr(MInst->getOpcode())) continue; // if there are any added instructions... @@ -573,11 +573,11 @@ void PhyRegAlloc::updateMachineCode() AddedInstrns &CallAI = AddedInstrMap[MInst]; #ifndef NDEBUG - bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) || - TM.getInstrInfo().isReturn(MInst->getOpcode())); + bool isBranch = (TM.getInstrInfo()->isBranch(MInst->getOpcode()) || + TM.getInstrInfo()->isReturn(MInst->getOpcode())); assert((!isBranch || AddedInstrMap[MInst].InstrnsAfter.size() <= - TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) && + TM.getInstrInfo()->getNumDelaySlots(MInst->getOpcode())) && "Cannot put more than #delaySlots instrns after " "branch or return! Need to handle temps differently."); #endif @@ -628,9 +628,9 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, MachineInstr *MInst = MII; const BasicBlock *BB = MBB.getBasicBlock(); - assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) && + assert((! TM.getInstrInfo()->isCall(MInst->getOpcode()) || OpNum == 0) && "Outgoing arg of a call must be handled elsewhere (func arg ok)"); - assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) && + assert(! TM.getInstrInfo()->isReturn(MInst->getOpcode()) && "Return value of a ret must be handled elsewhere"); MachineOperand& Op = MInst->getOperand(OpNum); @@ -649,7 +649,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, // trample those! Verify that the set is included in the LV set before MInst. if (MII != MBB.begin()) { MachineBasicBlock::iterator PredMI = prior(MII); - if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode())) + if (unsigned DS = TM.getInstrInfo()->getNumDelaySlots(PredMI->getOpcode())) assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef) .empty() && "Live-var set before branch should be included in " "live-var set of each delay slot instruction!"); @@ -735,7 +735,7 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore, std::vector<MachineInstr*> &instrnsAfter, MachineInstr *CallMI, const BasicBlock *BB) { - assert(TM.getInstrInfo().isCall(CallMI->getOpcode())); + assert(TM.getInstrInfo()->isCall(CallMI->getOpcode())); // hash set to record which registers were saved/restored hash_set<unsigned> PushedRegSet; @@ -1326,8 +1326,8 @@ bool PhyRegAlloc::runOnFunction (Function &F) { // Create each RegClass for the target machine and add it to the // RegClassList. This must be done before calling constructLiveRanges(). for (unsigned rc = 0; rc != NumOfRegClasses; ++rc) - RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (), - MRI.getMachineRegClass (rc))); + RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(), + MRI.getMachineRegClass(rc))); LRI->constructLiveRanges(); // create LR info if (DEBUG_RA >= RA_DEBUG_LiveRanges) diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h index 9e6070f9f4..65cc2e1f90 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h @@ -93,7 +93,7 @@ public: typedef std::map<const Function *, std::vector<AllocInfo> > SavedStateMapTy; inline PhyRegAlloc (const TargetMachine &TM_) : - TM (TM_), MRI (TM.getRegInfo ()), + TM (TM_), MRI (*TM.getRegInfo ()), NumOfRegClasses (MRI.getNumOfRegClasses ()) { } virtual ~PhyRegAlloc() { } diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp index 552902120a..6898704191 100644 --- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp +++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp @@ -74,6 +74,15 @@ namespace { arrayType->getElementType() == Type::SByteTy); } + unsigned findOptimalStorageSize(const TargetMachine &TM, const Type *Ty) { + // All integer types smaller than ints promote to 4 byte integers. + if (Ty->isIntegral() && Ty->getPrimitiveSize() < 4) + return 4; + + return TM.getTargetData().getTypeSize(Ty); + } + + inline const std::string TypeToDataDirective(const Type* type) { switch(type->getPrimitiveID()) @@ -111,7 +120,7 @@ namespace { return 1 + CVA->getNumOperands(); } - return target.findOptimalStorageSize(CV->getType()); + return findOptimalStorageSize(target, CV->getType()); } /// Align data larger than one L1 cache line on L1 cache line boundaries. @@ -132,7 +141,7 @@ namespace { /// inline unsigned int TypeToAlignment(const Type* type, const TargetMachine& target) { - return SizeToAlignment(target.findOptimalStorageSize(type), target); + return SizeToAlignment(findOptimalStorageSize(target, type), target); } /// Get the size of the constant and then use SizeToAlignment. @@ -580,9 +589,9 @@ SparcV9AsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI, inline bool SparcV9AsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI, unsigned int opNum) { - if (Target.getInstrInfo().isLoad(MI->getOpcode())) + if (Target.getInstrInfo()->isLoad(MI->getOpcode())) return (opNum == 0); - else if (Target.getInstrInfo().isStore(MI->getOpcode())) + else if (Target.getInstrInfo()->isStore(MI->getOpcode())) return (opNum == 1); else return false; @@ -639,11 +648,11 @@ SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop, { int regNum = (int)mop.getReg(); - if (regNum == Target.getRegInfo().getInvalidRegNum()) { + if (regNum == Target.getRegInfo()->getInvalidRegNum()) { // better to print code with NULL registers than to die toAsm << "<NULL VALUE>"; } else { - toAsm << "%" << Target.getRegInfo().getUnifiedRegName(regNum); + toAsm << "%" << Target.getRegInfo()->getUnifiedRegName(regNum); } break; } @@ -693,10 +702,10 @@ SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop, void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) { unsigned Opcode = MI->getOpcode(); - if (Target.getInstrInfo().isDummyPhiInstr(Opcode)) + if (Target.getInstrInfo()->isDummyPhiInstr(Opcode)) return; // IGNORE PHI NODES - toAsm << "\t" << Target.getInstrInfo().getName(Opcode) << "\t"; + toAsm << "\t" << Target.getInstrInfo()->getName(Opcode) << "\t"; unsigned Mask = getOperandMask(Opcode); @@ -770,7 +779,7 @@ void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) { Target) << "\n"; toAsm << "\t.type\t" << getID(GV) << ",#object\n"; toAsm << "\t.reserve\t" << getID(GV) << "," - << Target.findOptimalStorageSize(GV->getType()->getElementType()) + << findOptimalStorageSize(Target, GV->getType()->getElementType()) << "\n"; } } diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp index 4fc221325a..a11594e53b 100644 --- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp +++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp @@ -474,7 +474,7 @@ void SparcV9CodeEmitter::emitWord(unsigned Val) { unsigned SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, MachineInstr &MI) { - const TargetRegInfo &RI = TM.getRegInfo(); + const TargetRegInfo &RI = *TM.getRegInfo(); unsigned regClass, regType = RI.getRegType(fakeReg); // At least map fakeReg into its class fakeReg = RI.getClassRegNum(fakeReg, regClass); @@ -656,7 +656,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI, unsigned realRegByClass = getRealRegNum(fakeReg, MI); DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => " << realRegByClass << " (LLC: " - << TM.getRegInfo().getUnifiedRegName(fakeReg) << ")\n"); + << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n"); rv = realRegByClass; } else if (MO.isImmediate()) { rv = MO.getImmedValue(); diff --git a/lib/Target/SparcV9/SparcV9FrameInfo.h b/lib/Target/SparcV9/SparcV9FrameInfo.h index 97153f8f97..0a1bf207e3 100644 --- a/lib/Target/SparcV9/SparcV9FrameInfo.h +++ b/lib/Target/SparcV9/SparcV9FrameInfo.h @@ -72,22 +72,22 @@ public: // (generally FP or SP) // virtual int getIncomingArgBaseRegNum() const { - return (int) target.getRegInfo().getFramePointer(); + return (int) target.getRegInfo()->getFramePointer(); } virtual int getOutgoingArgBaseRegNum() const { - return (int) target.getRegInfo().getStackPointer(); + return (int) target.getRegInfo()->getStackPointer(); } virtual int getOptionalOutgoingArgBaseRegNum() const { - return (int) target.getRegInfo().getStackPointer(); + return (int) target.getRegInfo()->getStackPointer(); } virtual int getAutomaticVarBaseRegNum() const { - return (int) target.getRegInfo().getFramePointer(); + return (int) target.getRegInfo()->getFramePointer(); } virtual int getRegSpillAreaBaseRegNum() const { - return (int) target.getRegInfo().getFramePointer(); + return (int) target.getRegInfo()->getFramePointer(); } virtual int getDynamicAreaBaseRegNum() const { - return (int) target.getRegInfo().getStackPointer(); + return (int) target.getRegInfo()->getStackPointer(); } virtual int getIncomingArgOffset(MachineFunction& mcInfo, diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp index af5f69a3e7..cbbe154ccf 100644 --- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp +++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp @@ -174,8 +174,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C, } else { // unsigned or small signed value that fits in simm13 field of OR assert(smallNegValue || (C & ~MAXSIMM) == 0); - miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo() - .getZeroRegNum()) + miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()->getZeroRegNum()) .addSImm(sC).addRegDef(dest); } mvec.push_back(miOR); @@ -588,7 +587,7 @@ SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target, mvec, mcfi); } - unsigned FPReg = target.getRegInfo().getFramePointer(); + unsigned FPReg = target.getRegInfo()->getFramePointer(); unsigned StoreOpcode = ChooseStoreInstruction(storeType); StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode); mvec.push_back(BuildMI(StoreOpcode, 3) @@ -633,7 +632,7 @@ SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target, // int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val); - unsigned FPReg = target.getRegInfo().getFramePointer(); + unsigned FPReg = target.getRegInfo()->getFramePointer(); // Store instruction stores `val' to [%fp+offset]. // The store opCode is based only the source value being copied. @@ -699,8 +698,8 @@ SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target, if (loadConstantToReg) { // `src' is constant and cannot fit in immed field for the ADD // Insert instructions to "load" the constant into a register - target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest, - mvec, mcfi); + target.getInstrInfo()->CreateCodeToLoadConst(target, F, src, dest, + mvec, mcfi); } else { // Create a reg-to-reg copy instruction for the given type: // -- For FP values, create a FMOVS or FMOVD instruction diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp index a0cbb000bb..352122ccf2 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp +++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp @@ -592,12 +592,12 @@ CreateCodeToConvertFloatToInt(const TargetMachine& target, castDestType)); // Create the fpreg-to-intreg copy code - target.getInstrInfo().CreateCodeToCopyFloatToInt(target, F, destForCast, + target.getInstrInfo()->CreateCodeToCopyFloatToInt(target, F, destForCast, fpToIntCopyDest, mvec, mcfi); // Create the uint64_t to uint32_t conversion, if needed if (destI->getType() == Type::UIntTy) - target.getInstrInfo(). + target.getInstrInfo()-> CreateZeroExtensionInstructions(target, F, fpToIntCopyDest, destI, /*numLowBits*/ 32, mvec, mcfi); } @@ -743,7 +743,7 @@ static inline MachineInstr* CreateIntNegInstruction(const TargetMachine& target, Value* vreg) { - return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo().getZeroRegNum()) + return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo()->getZeroRegNum()) .addReg(vreg).addRegDef(vreg); } @@ -793,7 +793,7 @@ CreateShiftInstructions(const TargetMachine& target, if (shiftDest != destVal) { // extend the sign-bit of the result into all upper bits of dest assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?"); - target.getInstrInfo(). + target.getInstrInfo()-> CreateSignExtensionInstructions(target, F, shiftDest, destVal, 8*opSize, mvec, mcfi); } @@ -811,7 +811,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F, MachineCodeForInstruction& mcfi) { /* Use max. multiply cost, viz., cost of MULX */ - unsigned cost = target.getInstrInfo().minLatency(V9::MULXr); + unsigned cost = target.getInstrInfo()->minLatency(V9::MULXr); unsigned firstNewInstr = mvec.size(); Value* constOp = rval; @@ -826,7 +826,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F, if (resultType->isInteger() || isa<PointerType>(resultType)) { bool isValidConst; - int64_t C = (int64_t) target.getInstrInfo().ConvertConstantToIntType(target, + int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target, constOp, constOp->getType(), isValidConst); if (isValidConst) { unsigned pow; @@ -837,8 +837,8 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F, } if (C == 0 || C == 1) { - cost = target.getInstrInfo().minLatency(V9::ADDr); - unsigned Zero = target.getRegInfo().getZeroRegNum(); + cost = target.getInstrInfo()->minLatency(V9::ADDr); + unsigned Zero = target.getRegInfo()->getZeroRegNum(); MachineInstr* M; if (C == 0) M =BuildMI(V9::ADDr,3).addMReg(Zero).addMReg(Zero).addRegDef(destVal); @@ -873,7 +873,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F, if (firstNewInstr < mvec.size()) { cost = 0; for (unsigned i=firstNewInstr; i < mvec.size(); ++i) - cost += target.getInstrInfo().minLatency(mvec[i]->getOpcode()); + cost += target.getInstrInfo()->minLatency(mvec[i]->getOpcode()); } return cost; @@ -897,7 +897,7 @@ CreateCheapestMulConstInstruction(const TargetMachine &target, Constant* P = ConstantExpr::get(Instruction::Mul, cast<Constant>(lval), cast<Constant>(rval)); - target.getInstrInfo().CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi); + target.getInstrInfo()->CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi); } else if (isa<Constant>(rval)) // rval is constant, but not lval CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi); @@ -969,7 +969,7 @@ CreateDivConstInstruction(TargetMachine &target, return; Instruction* destVal = instrNode->getInstruction(); - unsigned ZeroReg = target.getRegInfo().getZeroRegNum(); + unsigned ZeroReg = target.getRegInfo()->getZeroRegNum(); // Cases worth optimizing are: // (1) Divide by 1 for any type: replace with copy (ADD or FMOV) @@ -980,7 +980,7 @@ CreateDivConstInstruction(TargetMachine &target, if (resultType->isInteger()) { unsigned pow; bool isValidConst; - int64_t C = (int64_t) target.getInstrInfo().ConvertConstantToIntType(target, + int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target, constOp, constOp->getType(), isValidConst); if (isValidConst) { bool needNeg = false; @@ -1089,13 +1089,13 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target, // compile time if the total size is a known constant. if (isa<Constant>(numElementsVal)) { bool isValid; - int64_t numElem = (int64_t) target.getInstrInfo(). + int64_t numElem = (int64_t) target.getInstrInfo()-> ConvertConstantToIntType(target, numElementsVal, numElementsVal->getType(), isValid); assert(isValid && "Unexpectedly large array dimension in alloca!"); int64_t total = numElem * tsize; - if (int extra= total % target.getFrameInfo().getStackFrameSizeAlignment()) - total += target.getFrameInfo().getStackFrameSizeAlignment() - extra; + if (int extra= total % target.getFrameInfo()->getStackFrameSizeAlignment()) + total += target.getFrameInfo()->getStackFrameSizeAlignment() - extra; totalSizeVal = ConstantSInt::get(Type::IntTy, total); } else { // The size is not a constant. Generate code to compute it and @@ -1133,10 +1133,10 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target, bool growUp; ConstantSInt* dynamicAreaOffset = ConstantSInt::get(Type::IntTy, - target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp)); + target.getFrameInfo()->getDynamicAreaOffset(mcInfo,growUp)); assert(! growUp && "Has SPARC v9 stack frame convention changed?"); - unsigned SPReg = target.getRegInfo().getStackPointer(); + unsigned SPReg = target.getRegInfo()->getStackPointer(); // Instruction 2: sub %sp, totalSizeVal -> %sp getMvec.push_back(BuildMI(V9::SUBr, 3).addMReg(SPReg).addReg(totalSizeVal) @@ -1180,8 +1180,8 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target, paddedSize, tsize * numElements); - if (((int)paddedSize) > 8 * target.getFrameInfo().getSizeOfEachArgOnStack() || - ! target.getInstrInfo().constantFitsInImmedField(V9::LDXi,offsetFromFP)) { + if (((int)paddedSize) > 8 * target.getFrameInfo()->getSizeOfEachArgOnStack() || + ! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) { CreateCodeForVariableSizeAlloca(target, result, tsize, ConstantSInt::get(Type::IntTy,numElements), getMvec); @@ -1196,7 +1196,7 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target, ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP); // Instruction 1: add %fp, offsetFromFP -> result - unsigned FPReg = target.getRegInfo().getFramePointer(); + unsigned FPReg = target.getRegInfo()->getFramePointer(); getMvec.push_back(BuildMI(V9::ADDr, 3).addMReg(FPReg).addReg(offsetVal) .addRegDef(result)); } @@ -1408,9 +1408,9 @@ static bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr, bool ignore; Function* func = cast<Function>(callInstr.getParent()->getParent()); int numFixedArgs = func->getFunctionType()->getNumParams(); - int fpReg |