aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--lib/Target/Mips/MipsInstrFPU.td8
-rw-r--r--lib/Target/Mips/MipsInstrInfo.td2
-rw-r--r--lib/Target/X86/X86InstrCompiler.td30
-rw-r--r--lib/Target/X86/X86InstrControl.td26
-rw-r--r--lib/Target/X86/X86InstrInfo.td2
5 files changed, 34 insertions, 34 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index dcab7cbf00..7844df9f40 100644
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -282,24 +282,24 @@ let Predicates = [NotN64, NotMips64, HasStandardEncoding] in {
}
// Indexed loads and stores.
-let Predicates = [HasMips32r2Or64, NotNaCl/*@LOCALMOD*/] in {
+let Predicates = [HasMips32r2Or64, IsNotNaCl/*@LOCALMOD*/] in {
def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load>;
def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store>;
}
-let Predicates = [HasMips32r2, NotMips64, NotNaCl/*@LOCALMOD*/] in {
+let Predicates = [HasMips32r2, NotMips64, IsNotNaCl/*@LOCALMOD*/] in {
def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load>;
def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store>;
}
-let Predicates = [HasMips64, NotN64, NotNaCl/*@LOCALMOD*/],
+let Predicates = [HasMips64, NotN64, IsNotNaCl/*@LOCALMOD*/],
DecoderNamespace="Mips64" in {
def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load>;
def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store>;
}
// n64
-let Predicates = [IsN64, NotNaCl/*@LOCALMOD*/], isCodeGenOnly=1 in {
+let Predicates = [IsN64, IsNotNaCl/*@LOCALMOD*/], isCodeGenOnly=1 in {
def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load>;
def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load>;
def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store>;
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index f6259cc269..3142ac94b1 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -175,7 +175,7 @@ def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
AssemblerPredicate<"!FeatureMips16">;
def IsNaCl : Predicate<"Subtarget.isTargetNaCl()">;
-def NotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
+def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
let Predicates = [HasStandardEncoding];
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index d8b0ba6d6c..1430863055 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -93,7 +93,7 @@ def VAARG_64 : I<0, Pseudo,
[(set GR64:$dst,
(X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
(implicit EFLAGS)]>,
- Requires<[NotNaCl]>;
+ Requires<[IsNotNaCl]>;
// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
// targets. These calls are needed to probe the stack when allocating more than
// 4k bytes in one go. Touching the stack at 4K increments is necessary to
@@ -399,7 +399,7 @@ let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
"# TLS_addr32",
[(X86tlsaddr tls32addr:$sym)]>,
- Requires<[In32BitMode, NotNaCl]>;
+ Requires<[In32BitMode, IsNotNaCl]>;
def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
"# TLS_base_addr32",
[(X86tlsbaseaddr tls32baseaddr:$sym)]>,
@@ -993,9 +993,9 @@ def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
// Direct PC relative function call for small code model. 32-bit displacement
// sign extended to 64-bit.
def : Pat<(X86call (i64 tglobaladdr:$dst)),
- (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotNaCl]>;
+ (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsNotNaCl]>;
def : Pat<(X86call (i64 texternalsym:$dst)),
- (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotNaCl]>;
+ (CALL64pcrel32 texternalsym:$dst)>, Requires<[IsNotNaCl]>;
// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
// can never use callee-saved registers. That is the purpose of the GR64_TC
@@ -1024,7 +1024,7 @@ def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
// callee-saved register.
def : Pat<(X86tcret (load addr:$dst), imm:$off),
(TCRETURNmi addr:$dst, imm:$off)>,
- Requires<[In32BitMode, IsNotPIC, NotNaCl]>;
+ Requires<[In32BitMode, IsNotPIC, IsNotNaCl]>;
def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
(TCRETURNdi texternalsym:$dst, imm:$off)>,
@@ -1036,29 +1036,29 @@ def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
(TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
- Requires<[In64BitMode, NotNaCl]>;
+ Requires<[In64BitMode, IsNotNaCl]>;
// Don't fold loads into X86tcret requiring more than 6 regs.
// There wouldn't be enough scratch registers for base+index.
def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
(TCRETURNmi64 addr:$dst, imm:$off)>,
- Requires<[In64BitMode, NotNaCl]>;
+ Requires<[In64BitMode, IsNotNaCl]>;
def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
(TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
- Requires<[In64BitMode, NotNaCl]>;
+ Requires<[In64BitMode, IsNotNaCl]>;
def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
(TCRETURNdi64 texternalsym:$dst, imm:$off)>,
- Requires<[In64BitMode, NotNaCl]>;
+ Requires<[In64BitMode, IsNotNaCl]>;
// Normal calls, with various flavors of addresses.
def : Pat<(X86call (i32 tglobaladdr:$dst)),
- (CALLpcrel32 tglobaladdr:$dst)>, Requires<[NotNaCl]>;
+ (CALLpcrel32 tglobaladdr:$dst)>, Requires<[IsNotNaCl]>;
def : Pat<(X86call (i32 texternalsym:$dst)),
- (CALLpcrel32 texternalsym:$dst)>, Requires<[NotNaCl]>;
+ (CALLpcrel32 texternalsym:$dst)>, Requires<[IsNotNaCl]>;
def : Pat<(X86call (i32 imm:$dst)),
- (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr, NotNaCl]>;
+ (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr, IsNotNaCl]>;
// Comparisons.
@@ -1483,19 +1483,19 @@ def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
- sub_8bit_hi))>, Requires<[NotNaCl]>;
+ sub_8bit_hi))>, Requires<[IsNotNaCl]>;
def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
sub_8bit_hi))>,
- Requires<[In64BitMode, NotNaCl]>;
+ Requires<[In64BitMode, IsNotNaCl]>;
def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
sub_8bit_hi))>,
- Requires<[In64BitMode, NotNaCl]>;
+ Requires<[In64BitMode, IsNotNaCl]>;
// (shl x, 1) ==> (add x, x)
diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td
index 0815e9b5b1..5dd04aad69 100644
--- a/lib/Target/X86/X86InstrControl.td
+++ b/lib/Target/X86/X86InstrControl.td
@@ -112,7 +112,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
[(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>;
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
- [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode,NotNaCl]>;
+ [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode,IsNotNaCl]>;
def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
[(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>;
@@ -126,7 +126,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
(ins i32imm:$off, i16imm:$seg),
"ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>;
def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
- "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>, Requires<[NotNaCl]>;
+ "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>, Requires<[IsNotNaCl]>;
def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
@@ -155,10 +155,10 @@ let isCall = 1 in
"call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>;
def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
- Requires<[In32BitMode,NotNaCl]>; // @LOCALMOD
+ Requires<[In32BitMode,IsNotNaCl]>; // @LOCALMOD
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>,
- Requires<[In32BitMode,NotNaCl]>; // @LOCALMOD
+ Requires<[In32BitMode,IsNotNaCl]>; // @LOCALMOD
def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
(ins i16imm:$off, i16imm:$seg),
@@ -179,7 +179,7 @@ let isCall = 1 in
def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
(outs), (ins i16imm_pcrel:$dst),
"callw\t$dst", []>, OpSize,
- Requires<[NotNaCl]>; // @LOCALMOD
+ Requires<[IsNotNaCl]>; // @LOCALMOD
}
// @LOCALMOD-BEGIN
@@ -188,9 +188,9 @@ let isCall = 1 in
// without disabling the the instruction itself. (so we can use the
// instruction in assembly input)
def : Pat<(X86call GR32:$dst),
- (CALL32r GR32:$dst)>, Requires<[NotNaCl]>;
+ (CALL32r GR32:$dst)>, Requires<[IsNotNaCl]>;
def : Pat<(X86call (loadi32 addr:$dst)),
- (CALL32m addr:$dst)>, Requires<[NotNaCl]>;
+ (CALL32m addr:$dst)>, Requires<[IsNotNaCl]>;
// @LOCALMOD-END
// Tail call stuff.
@@ -216,7 +216,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
"", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
let mayLoad = 1 in
def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
- "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>, Requires<[NotNaCl]>; // @LOCALMOD
+ "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>, Requires<[IsNotNaCl]>; // @LOCALMOD
}
@@ -234,18 +234,18 @@ let isCall = 1, Uses = [RSP] in {
def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
(outs), (ins i64i32imm_pcrel:$dst),
"call{q}\t$dst", [], IIC_CALL_RI>,
- Requires<[In64BitMode, NotNaCl]>; // @LOCALMOD
+ Requires<[In64BitMode, IsNotNaCl]>; // @LOCALMOD
def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
"call{q}\t{*}$dst", [(X86call GR64:$dst)],
IIC_CALL_RI>,
- Requires<[In64BitMode, NotNaCl]>; // @LOCALMOD
+ Requires<[In64BitMode, IsNotNaCl]>; // @LOCALMOD
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
IIC_CALL_MEM>,
- Requires<[In64BitMode, NotNaCl]>; // @LOCALMOD
+ Requires<[In64BitMode, IsNotNaCl]>; // @LOCALMOD
def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
- "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>, Requires<[NotNaCl]>; // @LOCALMOD
+ "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>, Requires<[IsNotNaCl]>; // @LOCALMOD
}
let isCall = 1, isCodeGenOnly = 1 in
@@ -281,5 +281,5 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
let mayLoad = 1 in
def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
"jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>,
- Requires<[NotNaCl]>; // @LOCALMOD
+ Requires<[IsNotNaCl]>; // @LOCALMOD
}
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index aff5defedb..73de7ce0d3 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -615,7 +615,7 @@ def In64BitMode : Predicate<"Subtarget->is64Bit()">,
AssemblerPredicate<"Mode64Bit">;
def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
-def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
+def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-03 21:01:57 +0000