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-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp5
-rw-r--r--test/MC/ARM/basic-thumb2-instructions.s9
2 files changed, 12 insertions, 2 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 614150dd09..dc310a183d 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3806,8 +3806,9 @@ processInstruction(MCInst &Inst,
// request the 32-bit variant, transform it here.
if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
Inst.getOperand(1).getImm() <= 255 &&
- Inst.getOperand(2).getImm() == ARMCC::AL &&
- Inst.getOperand(4).getReg() == ARM::CPSR &&
+ ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
+ Inst.getOperand(4).getReg() == ARM::CPSR) ||
+ (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
(!static_cast<ARMOperand*>(Operands[2])->isToken() ||
static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
// The operands aren't in the same order for tMOVi8...
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 5da74024bb..adedabd864 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -1009,6 +1009,10 @@ _func:
mov.w r0, #0x3fc0000
mov r0, #0x3fc0000
movs.w r0, #0x3fc0000
+ itte eq
+ movseq r1, #12
+ moveq r1, #12
+ movne.w r1, #12
@ CHECK: movs r1, #21 @ encoding: [0x15,0x21]
@ CHECK: movs.w r1, #21 @ encoding: [0x5f,0xf0,0x15,0x01]
@@ -1019,6 +1023,11 @@ _func:
@ CHECK: mov.w r0, #66846720 @ encoding: [0x4f,0xf0,0x7f,0x70]
@ CHECK: mov.w r0, #66846720 @ encoding: [0x4f,0xf0,0x7f,0x70]
@ CHECK: movs.w r0, #66846720 @ encoding: [0x5f,0xf0,0x7f,0x70]
+@ CHECK: itte eq @ encoding: [0x06,0xbf]
+@ CHECK: movseq.w r1, #12 @ encoding: [0x5f,0xf0,0x0c,0x01]
+@ CHECK: moveq r1, #12 @ encoding: [0x0c,0x21]
+@ CHECK: movne.w r1, #12 @ encoding: [0x4f,0xf0,0x0c,0x01]
+
@------------------------------------------------------------------------------