diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 14 | ||||
| -rw-r--r-- | test/CodeGen/X86/sse2-blend.ll | 8 |
2 files changed, 7 insertions, 15 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index a351fa5ca8..02c9f8ef22 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -10125,11 +10125,6 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) switch (VT.getSimpleVT().SimpleTy) { default: return SDValue(); - case MVT::v2i64: { - SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q; - SRAIntrinsicsID = 0; - break; - } case MVT::v4i32: { SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; @@ -10149,12 +10144,9 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) // In case of 1 bit sext, no need to shr if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; - if (SRAIntrinsicsID) { - Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(SRAIntrinsicsID, MVT::i32), - Tmp1, ShAmt); - } - return Tmp1; + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(SRAIntrinsicsID, MVT::i32), + Tmp1, ShAmt); } return SDValue(); diff --git a/test/CodeGen/X86/sse2-blend.ll b/test/CodeGen/X86/sse2-blend.ll index 1c86b31a8b..56b099ec42 100644 --- a/test/CodeGen/X86/sse2-blend.ll +++ b/test/CodeGen/X86/sse2-blend.ll @@ -24,8 +24,8 @@ define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) { ; CHECK: vsel_i64 ; CHECK: pxor ; CHECK: pand -; CHECK: pandn -; CHECK: por +; CHECK: andnps +; CHECK: orps ; CHECK: ret define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) { @@ -39,8 +39,8 @@ define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) { ; CHECK: vsel_double ; CHECK: pxor ; CHECK: pand -; CHECK: pandn -; CHECK: por +; CHECK: andnps +; CHECK: orps ; CHECK: ret |