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-rw-r--r--include/llvm/CodeGen/ISDOpcodes.h1
-rw-r--r--include/llvm/Intrinsics.td3
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp5
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp1
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp12
-rw-r--r--lib/Target/ARM/ARMISelLowering.h1
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp8
-rw-r--r--lib/Target/Mips/MipsISelLowering.h1
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp13
-rw-r--r--lib/Target/X86/X86ISelLowering.h1
10 files changed, 0 insertions, 46 deletions
diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h
index 948227e828..68fcb3e17b 100644
--- a/include/llvm/CodeGen/ISDOpcodes.h
+++ b/include/llvm/CodeGen/ISDOpcodes.h
@@ -641,7 +641,6 @@ namespace ISD {
// NACL_* - Native Client instrinsics.
// These correspond to functions in:
// native_client/src/untrusted/nacl/tls_params.h
- NACL_THREAD_STACK_PADDING,
NACL_TP_ALIGN,
NACL_TP_TLS_OFFSET,
NACL_TP_TDB_OFFSET,
diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td
index 47933f451a..e9a4e3aaaf 100644
--- a/include/llvm/Intrinsics.td
+++ b/include/llvm/Intrinsics.td
@@ -471,9 +471,6 @@ def int_nacl_tp_tls_offset : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>,
GCCBuiltin<"__builtin_nacl_tp_tls_offset">;
def int_nacl_tp_tdb_offset : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>,
GCCBuiltin<"__builtin_nacl_tp_tdb_offset">;
-def int_nacl_thread_stack_padding :
- Intrinsic<[llvm_i32_ty], []>,
- GCCBuiltin<"__builtin_nacl_thread_stack_padding">;
// The following intrinsic provides a target-specific constant value to
// indicate the target platform compiled to. The enum values are enumerated
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index e0a061d8be..2783664e53 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5195,11 +5195,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
return 0;
// @LOCALMOD-BEGIN
// Native Client Intrinsics for TLS setup / layout.
- case Intrinsic::nacl_thread_stack_padding: {
- EVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getNode(ISD::NACL_THREAD_STACK_PADDING, dl, DestVT));
- return 0;
- }
case Intrinsic::nacl_tp_alignment: {
EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::NACL_TP_ALIGN, dl, DestVT));
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 1c357ef375..b6f2ff410d 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -314,7 +314,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
// @LOCALMOD-BEGIN
// NaCl intrinsics for TLS setup
- case ISD::NACL_THREAD_STACK_PADDING: return "nacl_thread_stack_padding";
case ISD::NACL_TP_ALIGN: return "nacl_tp_alignment";
case ISD::NACL_TP_TLS_OFFSET: return "nacl_tls_offset";
case ISD::NACL_TP_TDB_OFFSET: return "nacl_tdb_offset";
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 0d1139fcd9..bd00f4b7ef 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -816,7 +816,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
// @LOCALMOD-BEGIN
if (Subtarget->isTargetNaCl()) {
- setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_ALIGN, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_TLS_OFFSET, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_TDB_OFFSET, MVT::i32, Custom);
@@ -2185,15 +2184,6 @@ SDValue ARMTargetLowering::LowerNaClTpTdbOffset(SDValue Op,
}
SDValue
-ARMTargetLowering::LowerNaClThreadStackPadding(SDValue Op,
- SelectionDAG &DAG) const {
- // size_t __nacl_thread_stack_padding () {
- // return 0;
- // }
- return DAG.getConstant(0, Op.getValueType().getSimpleVT());
-}
-
-SDValue
ARMTargetLowering::LowerNaClTargetArch(SDValue Op, SelectionDAG &DAG) const {
// size_t __nacl_target_arch () {
// return PnaclTargetArchitectureARM_32;
@@ -5504,8 +5494,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ATOMIC_LOAD:
case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
// @LOCALMOD-BEGIN
- case ISD::NACL_THREAD_STACK_PADDING:
- return LowerNaClThreadStackPadding(Op, DAG);
case ISD::NACL_TP_ALIGN: return LowerNaClTpAlign(Op, DAG);
case ISD::NACL_TP_TLS_OFFSET: return LowerNaClTpTlsOffset(Op, DAG);
case ISD::NACL_TP_TDB_OFFSET: return LowerNaClTpTdbOffset(Op, DAG);
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 62d3166024..2cf26ba1af 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -432,7 +432,6 @@ namespace llvm {
// @LOCALMOD-START
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerNaClThreadStackPadding(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpAlign(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpTlsOffset(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpTdbOffset(SDValue Op, SelectionDAG &DAG) const;
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 581d53117b..1a656c97d8 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -289,7 +289,6 @@ MipsTargetLowering(MipsTargetMachine &TM)
// @LOCALMOD-BEGIN
if (Subtarget->isTargetNaCl()) {
- setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_ALIGN, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_TLS_OFFSET, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_TDB_OFFSET, MVT::i32, Custom);
@@ -822,8 +821,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
case ISD::STORE: return LowerSTORE(Op, DAG);
// @LOCALMOD-BEGIN
- case ISD::NACL_THREAD_STACK_PADDING:
- return LowerNaClThreadStackPadding(Op, DAG);
case ISD::NACL_TP_ALIGN: return LowerNaClTpAlign(Op, DAG);
case ISD::NACL_TP_TLS_OFFSET: return LowerNaClTpTlsOffset(Op, DAG);
case ISD::NACL_TP_TDB_OFFSET: return LowerNaClTpTdbOffset(Op, DAG);
@@ -1662,11 +1659,6 @@ SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
// NaCl TLS setup / layout intrinsics.
// See: native_client/src/untrusted/nacl/tls_params.h
-SDValue MipsTargetLowering::LowerNaClThreadStackPadding(SDValue Op,
- SelectionDAG &DAG) const {
- return DAG.getConstant(0, Op.getValueType().getSimpleVT());
-}
-
SDValue MipsTargetLowering::LowerNaClTpAlign(SDValue Op,
SelectionDAG &DAG) const {
return DAG.getConstant(4, Op.getValueType().getSimpleVT());
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 5abf77dc65..e23752c62a 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -153,7 +153,6 @@ namespace llvm {
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
// @LOCALMOD-BEGIN
- SDValue LowerNaClThreadStackPadding(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpAlign(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpTlsOffset(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpTdbOffset(SDValue Op, SelectionDAG &DAG) const;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index ca70f44fdc..294a4ed1f3 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1238,7 +1238,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// @LOCALMOD-BEGIN
if (Subtarget->isTargetNaCl()) {
- setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_ALIGN, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_TLS_OFFSET, MVT::i32, Custom);
setOperationAction(ISD::NACL_TP_TDB_OFFSET, MVT::i32, Custom);
@@ -9652,16 +9651,6 @@ SDValue X86TargetLowering::LowerNaClTpTdbOffset(SDValue Op,
}
SDValue
-X86TargetLowering::LowerNaClThreadStackPadding(SDValue Op,
- SelectionDAG &DAG) const {
- // size_t __nacl_thread_stack_padding () {
- // return reg_size;
- // }
- return DAG.getConstant(RegInfo->getSlotSize(),
- Op.getValueType().getSimpleVT());
-}
-
-SDValue
X86TargetLowering::LowerNaClTargetArch(SDValue Op, SelectionDAG &DAG) const {
// int __nacl_target_arch () {
// return (is_64_bit ?
@@ -11403,8 +11392,6 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADD: return LowerADD(Op, DAG);
case ISD::SUB: return LowerSUB(Op, DAG);
// @LOCALMOD-BEGIN
- case ISD::NACL_THREAD_STACK_PADDING:
- return LowerNaClThreadStackPadding(Op, DAG);
case ISD::NACL_TP_ALIGN: return LowerNaClTpAlign(Op, DAG);
case ISD::NACL_TP_TLS_OFFSET: return LowerNaClTpTlsOffset(Op, DAG);
case ISD::NACL_TP_TDB_OFFSET: return LowerNaClTpTdbOffset(Op, DAG);
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index ee0f776103..e5bbf15cdf 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -838,7 +838,6 @@ namespace llvm {
SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const;
// @LOCALMOD-BEGIN
- SDValue LowerNaClThreadStackPadding(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpAlign(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpTlsOffset(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerNaClTpTdbOffset(SDValue Op, SelectionDAG &DAG) const;
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-05 13:55:51 +0000