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-rw-r--r--docs/CodeGenerator.html2
-rw-r--r--include/llvm/CodeGen/MachineInstrBuilder.h56
-rw-r--r--lib/CodeGen/TargetInstrInfoImpl.cpp6
-rw-r--r--lib/Target/ARM/ARMInstrInfo.cpp26
-rw-r--r--lib/Target/ARM/ARMLoadStoreOptimizer.cpp19
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.cpp30
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.cpp12
-rw-r--r--lib/Target/CellSPU/SPUInstrInfo.cpp8
-rw-r--r--lib/Target/IA64/IA64InstrInfo.cpp8
-rw-r--r--lib/Target/MSP430/MSP430InstrInfo.cpp6
-rw-r--r--lib/Target/MSP430/MSP430RegisterInfo.cpp2
-rw-r--r--lib/Target/Mips/MipsInstrInfo.cpp12
-rw-r--r--lib/Target/PIC16/PIC16InstrInfo.cpp4
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.cpp64
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp40
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.cpp12
-rw-r--r--lib/Target/X86/X86InstrBuilder.h8
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp74
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp4
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.cpp2
-rw-r--r--lib/Target/XCore/XCoreRegisterInfo.cpp12
21 files changed, 242 insertions, 165 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index dd9cd4a45b..9a28f1f0ca 100644
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -600,7 +600,7 @@ BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
<div class="doc_code">
<pre>
-MI.addReg(Reg, MachineOperand::Def);
+MI.addReg(Reg, RegState::Define);
</pre>
</div>
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index de27bc74ee..d3a09959a1 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -23,6 +23,18 @@ namespace llvm {
class TargetInstrDesc;
+namespace RegState {
+ enum {
+ Define = 0x2,
+ Implicit = 0x4,
+ Kill = 0x8,
+ Dead = 0x10,
+ EarlyClobber = 0x20,
+ ImplicitDefine = Implicit | Define,
+ ImplicitKill = Implicit | Kill
+ };
+}
+
class MachineInstrBuilder {
MachineInstr *MI;
public:
@@ -36,12 +48,17 @@ public:
/// addReg - Add a new virtual register operand...
///
const
- MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false,
- bool isImp = false, bool isKill = false,
- bool isDead = false, unsigned SubReg = 0,
- bool isEarlyClobber = false) const {
- MI->addOperand(MachineOperand::CreateReg(RegNo, isDef, isImp, isKill,
- isDead, SubReg, isEarlyClobber));
+ MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
+ unsigned SubReg = 0) const {
+ assert((flags & 0x1) == 0 &&
+ "Passing in 'true' to addReg is forbidden! Use enums instead.");
+ MI->addOperand(MachineOperand::CreateReg(RegNo,
+ flags & RegState::Define,
+ flags & RegState::Implicit,
+ flags & RegState::Kill,
+ flags & RegState::Dead,
+ SubReg,
+ flags & RegState::EarlyClobber));
return *this;
}
@@ -97,9 +114,13 @@ public:
const MachineInstrBuilder &addOperand(const MachineOperand &MO) const {
if (MO.isReg())
- return addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
- MO.isKill(), MO.isDead(), MO.getSubReg(),
- MO.isEarlyClobber());
+ return addReg(MO.getReg(),
+ (MO.isDef() ? RegState::Define : 0) |
+ (MO.isImplicit() ? RegState::Implicit : 0) |
+ (MO.isKill() ? RegState::Kill : 0) |
+ (MO.isDead() ? RegState::Dead : 0) |
+ (MO.isEarlyClobber() ? RegState::EarlyClobber : 0),
+ MO.getSubReg());
if (MO.isImm())
return addImm(MO.getImm());
if (MO.isFI())
@@ -135,7 +156,7 @@ inline MachineInstrBuilder BuildMI(MachineFunction &MF,
const TargetInstrDesc &TID,
unsigned DestReg) {
return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL))
- .addReg(DestReg, true);
+ .addReg(DestReg, RegState::Define);
}
/// BuildMI - This version of the builder inserts the newly-built
@@ -149,7 +170,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
unsigned DestReg) {
MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL);
BB.insert(I, MI);
- return MachineInstrBuilder(MI).addReg(DestReg, true);
+ return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
}
/// BuildMI - This version of the builder inserts the newly-built
@@ -186,6 +207,19 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
return BuildMI(*BB, BB->end(), DL, TID, DestReg);
}
+inline unsigned getDefRegState(bool B) {
+ return B ? RegState::Define : 0;
+}
+inline unsigned getImplRegState(bool B) {
+ return B ? RegState::Implicit : 0;
+}
+inline unsigned getKillRegState(bool B) {
+ return B ? RegState::Kill : 0;
+}
+inline unsigned getDeadRegState(bool B) {
+ return B ? RegState::Dead : 0;
+}
+
} // End llvm namespace
#endif
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index a213400dcb..a5e1ee4355 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -45,9 +45,9 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
bool Reg0IsDead = MI->getOperand(0).isDead();
MachineFunction &MF = *MI->getParent()->getParent();
return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
- .addReg(Reg0, true, false, false, Reg0IsDead)
- .addReg(Reg2, false, false, Reg2IsKill)
- .addReg(Reg1, false, false, Reg1IsKill);
+ .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
+ .addReg(Reg2, getKillRegState(Reg2IsKill))
+ .addReg(Reg1, getKillRegState(Reg2IsKill));
}
if (ChangeReg0)
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 235d1d1d50..8e678a8c46 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -546,23 +546,23 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert (!AFI->isThumbFunction());
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::tGPRRegisterClass) {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert (AFI->isThumbFunction());
BuildMI(MBB, I, DL, get(ARM::tSpill))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0);
} else if (RC == ARM::DPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0));
} else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0));
}
}
@@ -579,7 +579,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
if (AFI->isThumbFunction()) {
Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
MachineInstrBuilder MIB =
- BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
@@ -594,7 +594,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
}
MachineInstrBuilder MIB =
- BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
AddDefaultPred(MIB);
@@ -681,7 +681,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
- MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
+ MIB.addReg(Reg, RegState::Kill);
}
return true;
}
@@ -733,13 +733,13 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
}
break;
@@ -755,7 +755,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
// tSpill cannot take a high register operand.
break;
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
@@ -764,7 +764,7 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
break;
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addImm(0);
}
break;
@@ -792,13 +792,13 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
}
break;
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 710bc3e90e..047552f627 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -159,7 +159,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
return false; // Probably not worth it then.
BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
- .addReg(Base, false, false, BaseKill).addImm(ImmedOffset)
+ .addReg(Base, getKillRegState(BaseKill)).addImm(ImmedOffset)
.addImm(Pred).addReg(PredReg).addReg(0);
Base = NewBase;
BaseKill = true; // New base is always killed right its use.
@@ -170,14 +170,15 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
Opcode = getLoadStoreMultipleOpcode(Opcode);
MachineInstrBuilder MIB = (isAM4)
? BuildMI(MBB, MBBI, dl, TII->get(Opcode))
- .addReg(Base, false, false, BaseKill)
+ .addReg(Base, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
: BuildMI(MBB, MBBI, dl, TII->get(Opcode))
- .addReg(Base, false, false, BaseKill)
+ .addReg(Base, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
.addImm(Pred).addReg(PredReg);
for (unsigned i = 0; i != NumRegs; ++i)
- MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second);
+ MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
+ | getKillRegState(Regs[i].second));
return true;
}
@@ -516,26 +517,26 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
if (isAM2)
// LDR_PRE, LDR_POST;
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
- .addReg(Base, true)
+ .addReg(Base, RegState::Define)
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
else
// FLDMS, FLDMD
BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
- .addReg(Base, false, false, BaseKill)
+ .addReg(Base, getKillRegState(BaseKill))
.addImm(Offset).addImm(Pred).addReg(PredReg)
- .addReg(MI->getOperand(0).getReg(), true);
+ .addReg(MI->getOperand(0).getReg(), RegState::Define);
} else {
MachineOperand &MO = MI->getOperand(0);
if (isAM2)
// STR_PRE, STR_POST;
BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
- .addReg(MO.getReg(), false, false, MO.isKill())
+ .addReg(MO.getReg(), getKillRegState(BaseKill))
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
else
// FSTMS, FSTMD
BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset)
.addImm(Pred).addReg(PredReg)
- .addReg(MO.getReg(), false, false, MO.isKill());
+ .addReg(MO.getReg(), getKillRegState(MO.isKill()));
}
MBB.erase(MBBI);
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 2fae432633..693d12ee1f 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -368,7 +368,7 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
// Build the new ADD / SUB.
BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
- .addReg(BaseReg, false, false, true).addImm(SOImmVal)
+ .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
BaseReg = DestReg;
}
@@ -426,7 +426,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
assert(BaseReg == ARM::SP && "Unexpected!");
LdReg = ARM::R3;
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
- .addReg(ARM::R3, false, false, true);
+ .addReg(ARM::R3, RegState::Kill);
}
if (NumBytes <= 255 && NumBytes >= 0)
@@ -434,7 +434,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
else if (NumBytes < 0 && NumBytes >= -255) {
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
- .addReg(LdReg, false, false, true);
+ .addReg(LdReg, RegState::Kill);
} else
MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII,
true, dl);
@@ -444,12 +444,12 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
TII.get(Opc), DestReg);
if (DestReg == ARM::SP || isSub)
- MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
+ MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
else
- MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
+ MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
if (DestReg == ARM::SP)
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
- .addReg(ARM::R12, false, false, true);
+ .addReg(ARM::R12, RegState::Kill);
}
/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
@@ -518,10 +518,10 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
Bytes -= ThisVal;
BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
- .addReg(BaseReg, false, false, true).addImm(ThisVal);
+ .addReg(BaseReg, RegState::Kill).addImm(ThisVal);
} else {
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
- .addReg(BaseReg, false, false, true);
+ .addReg(BaseReg, RegState::Kill);
}
BaseReg = DestReg;
}
@@ -538,7 +538,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
else {
bool isKill = BaseReg != ARM::SP;
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
- .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
+ .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
BaseReg = DestReg;
if (Opc == ARM::tADDrSPi) {
@@ -556,7 +556,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
if (ExtraOpc)
BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
- .addReg(DestReg, false, false, true)
+ .addReg(DestReg, RegState::Kill)
.addImm(((unsigned)NumBytes) & 3);
}
@@ -631,7 +631,7 @@ static void emitThumbConstant(MachineBasicBlock &MBB,
emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
if (isSub)
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
- .addReg(DestReg, false, false, true);
+ .addReg(DestReg, RegState::Kill);
}
/// findScratchRegister - Find a 'free' ARM register. If register scavenger
@@ -918,12 +918,12 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
bool UseRR = false;
if (ValReg == ARM::R3) {
BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
- .addReg(ARM::R2, false, false, true);
+ .addReg(ARM::R2, RegState::Kill);
TmpReg = ARM::R2;
}
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
- .addReg(ARM::R3, false, false, true);
+ .addReg(ARM::R3, RegState::Kill);
if (Opcode == ARM::tSpill) {
if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
@@ -946,10 +946,10 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineBasicBlock::iterator NII = next(II);
if (ValReg == ARM::R3)
BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
- .addReg(ARM::R12, false, false, true);
+ .addReg(ARM::R12, RegState::Kill);
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
- .addReg(ARM::R12, false, false, true);
+ .addReg(ARM::R12, RegState::Kill);
} else
assert(false && "Unexpected opcode!");
} else {
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 27408e2c79..a54d97d33c 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -187,15 +187,15 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, DL, get(Alpha::STS))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, DL, get(Alpha::STT))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, DL, get(Alpha::STQ))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
abort();
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB =
- BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
@@ -290,7 +290,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
- .addReg(InReg, false, false, isKill)
+ .addReg(InReg, getKillRegState(isKill))
.addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
@@ -299,7 +299,7 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
- .addReg(OutReg, true, false, false, isDead)
+ .addReg(OutReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 135164f3d9..92ca244ed4 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -320,7 +320,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
addFrameReference(BuildMI(MBB, MI, DL, get(opc))
- .addReg(SrcReg, false, false, isKill), FrameIdx);
+ .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
}
void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
@@ -353,7 +353,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
- .addReg(SrcReg, false, false, isKill);
+ .addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
@@ -495,7 +495,7 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
get(SPU::STQDr32));
- MIB.addReg(InReg, false, false, isKill);
+ MIB.addReg(InReg, getKillRegState(isKill));
NewMI = addFrameReference(MIB, FrameIndex);
}
} else { // move -> load
@@ -503,7 +503,7 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
bool isDead = MI->getOperand(0).isDead();
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
- MIB.addReg(OutReg, true, false, false, isDead);
+ MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead));
Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
? SPU::STQDr32 : SPU::STQXr32;
NewMI = addFrameReference(MIB, FrameIndex);
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index 65eff25261..5f89d4f139 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -96,17 +96,17 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (RC == IA64::FPRegisterClass) {
BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
- .addReg(SrcReg, false, false, isKill);
+ .addReg(SrcReg, getKillRegState(isKill));
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx)
- .addReg(SrcReg, false, false, isKill);
+ .addReg(SrcReg, getKillRegState(isKill));
} else if (RC == IA64::PRRegisterClass) {
/* we use IA64::r2 as a temporary register for doing this hackery. */
// first we load 0:
BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
// then conditionally add 1:
BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
- .addImm(1).addReg(SrcReg, false, false, isKill);
+ .addImm(1).addReg(SrcReg, getKillRegState(isKill));
// and then store it to the stack
BuildMI(MBB, MI, DL, get(IA64::ST8))
.addFrameIndex(FrameIdx)
@@ -136,7 +136,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
- MIB.addReg(SrcReg, false, false, isKill);
+ MIB.addReg(SrcReg, getKillRegState(isKill));
NewMIs.push_back(MIB);
return;
diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp
index 39c835d92f..91112c3d73 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -38,11 +38,11 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (RC == &MSP430::GR16RegClass)
BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
.addFrameIndex(FrameIdx).addImm(0)
- .addReg(SrcReg, false, false, isKill);
+ .addReg(SrcReg, getKillRegState(isKill));
else if (RC == &MSP430::GR8RegClass)
BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
.addFrameIndex(FrameIdx).addImm(0)
- .addReg(SrcReg, false, false, isKill);
+ .addReg(SrcReg, getKillRegState(isKill));
else
assert(0 && "Cannot store this register to stack slot!");
}
@@ -129,7 +129,7 @@ MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
- .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
+ .addReg(Reg, RegState::Kill);
}
return true;
}
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp
index ebd09fb78e..ef6f99756c 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -241,7 +241,7 @@ void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
// Save FPW into the appropriate stack slot...
BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
- .addReg(MSP430::FPW, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
+ .addReg(MSP430::FPW, RegState::Kill);
// Update FPW with the new base value...
BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index e5876e4019..2ccbe898fa 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -197,7 +197,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Opc = Mips::SDC1;
}
- BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill)
+ BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
}
@@ -217,7 +217,7 @@ void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
- .addReg(SrcReg, false, false, isKill);
+ .addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
@@ -285,13 +285,13 @@ foldMemoryOperandImpl(MachineFunction &MF,
unsigned SrcReg = MI->getOperand(2).getReg();
bool isKill = MI->getOperand(2).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addImm(0).addFrameIndex(FI);
}
}
@@ -315,13 +315,13 @@ foldMemoryOperandImpl(MachineFunction &MF,
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI) ;
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addImm(0).addFrameIndex(FI);
}
}
diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp
index c8cab3407d..2a769e8ad1 100644
--- a/lib/Target/PIC16/PIC16InstrInfo.cpp
+++ b/lib/Target/PIC16/PIC16InstrInfo.cpp
@@ -83,7 +83,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
//MachineFunction &MF = *MBB.getParent();
//MachineRegisterInfo &RI = MF.getRegInfo();
BuildMI(MBB, I, DL, get(PIC16::movwf))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addImm(PTLI->GetTmpOffsetForFI(FI, 1))
.addExternalSymbol(tmpName)
.addImm(1); // Emit banksel for it.
@@ -98,7 +98,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0
: PIC16::save_fsr1;
BuildMI(MBB, I, DL, get(opcode))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addImm(PTLI->GetTmpOffsetForFI(FI, 3))
.addExternalSymbol(tmpName)
.addImm(1); // Emit banksel for it.
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 81ff6c0507..778f0349d1 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -175,9 +175,9 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
bool Reg0IsDead = MI->getOperand(0).isDead();
return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
- .addReg(Reg0, true, false, false, Reg0IsDead)
- .addReg(Reg2, false, false, Reg2IsKill)
- .addReg(Reg1, false, false, Reg1IsKill)
+ .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
+ .addReg(Reg2, getKillRegState(Reg2IsKill))
+ .addReg(Reg1, getKillRegState(Reg1IsKill))
.addImm((ME+1) & 31)
.addImm((MB-1) & 31);
}
@@ -370,7 +370,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) {
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
- .addReg(SrcReg, false, false, isKill),
+ .addReg(SrcReg,
+ getKillRegState(isKill)),
FrameIdx));
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
@@ -378,33 +379,43 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
// a hack.
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
- .addReg(PPC::R11, false, false, isKill),
+ .addReg(PPC::R11,
+ getKillRegState(isKill)),
FrameIdx));
}
} else if (RC == PPC::G8RCRegisterClass) {
if (SrcReg != PPC::LR8) {
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
- .addReg(SrcReg, false, false, isKill), FrameIdx));
+ .addReg(SrcReg,
+ getKillRegState(isKill)),
+ FrameIdx));
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack.
NewMIs.push_back(BuildMI(MF, DL, get(PPC::MF