diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vext.ll | 17 |
2 files changed, 25 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f1000de429..6ead63f5ca 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4057,6 +4057,14 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, // A shuffle can only come from building a vector from various // elements of other vectors. return SDValue(); + } else if (V.getOperand(0).getValueType().getVectorElementType() != + VT.getVectorElementType()) { + // This code doesn't know how to handle shuffles where the vector + // element types do not match (this happens because type legalization + // promotes the return type of EXTRACT_VECTOR_ELT). + // FIXME: It might be appropriate to extend this code to handle + // mismatched types. + return SDValue(); } // Record this extraction against the appropriate vector if possible... diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 49a042b7e1..65b5913e40 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -133,3 +133,20 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9> ret <8 x i16> %tmp3 } + +; PR11129 +; Make sure this doesn't crash +define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind { +; CHECK: test_elem_mismatch: +; CHECK: vstr.64 + %tmp0 = load <2 x i64>* %src, align 16 + %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32> + %tmp2 = extractelement <4 x i32> %tmp1, i32 0 + %tmp3 = extractelement <4 x i32> %tmp1, i32 2 + %tmp4 = trunc i32 %tmp2 to i16 + %tmp5 = trunc i32 %tmp3 to i16 + %tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0 + %tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1 + store <4 x i16> %tmp7, <4 x i16>* %dest, align 4 + ret void +} |