diff options
22 files changed, 7879 insertions, 685 deletions
diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index af9e8136bf..29cf8a76c4 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -28,6 +28,7 @@ add_llvm_target(HexagonCodeGen HexagonSubtarget.cpp HexagonTargetMachine.cpp HexagonTargetObjectFile.cpp + HexagonVLIWPacketizer.cpp ) add_subdirectory(TargetInfo) diff --git a/lib/Target/Hexagon/Hexagon.h b/lib/Target/Hexagon/Hexagon.h index 0808323336..43858b9624 100644 --- a/lib/Target/Hexagon/Hexagon.h +++ b/lib/Target/Hexagon/Hexagon.h @@ -40,6 +40,7 @@ namespace llvm { FunctionPass *createHexagonHardwareLoops(); FunctionPass *createHexagonPeephole(); FunctionPass *createHexagonFixupHwLoops(); + FunctionPass *createHexagonPacketizer(); /* TODO: object output. MCCodeEmitter *createHexagonMCCodeEmitter(const Target &, diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 39bf45d2d7..63d58d0db9 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -13,11 +13,11 @@ // //===----------------------------------------------------------------------===// - #define DEBUG_TYPE "asm-printer" #include "Hexagon.h" #include "HexagonAsmPrinter.h" #include "HexagonMachineFunctionInfo.h" +#include "HexagonMCInst.h" #include "HexagonTargetMachine.h" #include "HexagonSubtarget.h" #include "InstPrinter/HexagonInstPrinter.h" @@ -54,6 +54,7 @@ #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" +#include <map> using namespace llvm; @@ -77,8 +78,7 @@ void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { - default: - assert(0 && "<unknown operand type>"); + default: llvm_unreachable ("<unknown operand type>"); case MachineOperand::MO_Register: O << HexagonInstPrinter::getRegisterName(MO.getReg()); return; @@ -196,10 +196,45 @@ void HexagonAsmPrinter::printPredicateOperand(const MachineInstr *MI, /// the current output stream. /// void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { - MCInst MCI; - - HexagonLowerToMC(MI, MCI, *this); - OutStreamer.EmitInstruction(MCI); + if (MI->isBundle()) { + std::vector<const MachineInstr*> BundleMIs; + + const MachineBasicBlock *MBB = MI->getParent(); + MachineBasicBlock::const_instr_iterator MII = MI; + ++MII; + unsigned int IgnoreCount = 0; + while (MII != MBB->end() && MII->isInsideBundle()) { + const MachineInstr *MInst = MII; + if (MInst->getOpcode() == TargetOpcode::DBG_VALUE || + MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) { + IgnoreCount++; + ++MII; + continue; + } + //BundleMIs.push_back(&*MII); + BundleMIs.push_back(MInst); + ++MII; + } + unsigned Size = BundleMIs.size(); + assert((Size+IgnoreCount) == MI->getBundleSize() && "Corrupt Bundle!"); + for (unsigned Index = 0; Index < Size; Index++) { + HexagonMCInst MCI; + MCI.setStartPacket(Index == 0); + MCI.setEndPacket(Index == (Size-1)); + + HexagonLowerToMC(BundleMIs[Index], MCI, *this); + OutStreamer.EmitInstruction(MCI); + } + } + else { + HexagonMCInst MCI; + if (MI->getOpcode() == Hexagon::ENDLOOP0) { + MCI.setStartPacket(true); + MCI.setEndPacket(true); + } + HexagonLowerToMC(MI, MCI, *this); + OutStreamer.EmitInstruction(MCI); + } return; } @@ -242,17 +277,17 @@ void HexagonAsmPrinter::printJumpTable(const MachineInstr *MI, int OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); assert( (MO.getType() == MachineOperand::MO_JumpTableIndex) && - "Expecting jump table index"); + "Expecting jump table index"); // Hexagon_TODO: Do we need name mangling? O << *GetJTISymbol(MO.getIndex()); } void HexagonAsmPrinter::printConstantPool(const MachineInstr *MI, int OpNo, - raw_ostream &O) { + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); assert( (MO.getType() == MachineOperand::MO_ConstantPoolIndex) && - "Expecting constant pool index"); + "Expecting constant pool index"); // Hexagon_TODO: Do we need name mangling? O << *GetCPISymbol(MO.getIndex()); diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index c9f16fb538..e3fa0edd79 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -13,13 +13,26 @@ // *** Must match HexagonBaseInfo.h *** //===----------------------------------------------------------------------===// +class Type<bits<5> t> { + bits<5> Value = t; +} +def TypePSEUDO : Type<0>; +def TypeALU32 : Type<1>; +def TypeCR : Type<2>; +def TypeJR : Type<3>; +def TypeJ : Type<4>; +def TypeLD : Type<5>; +def TypeST : Type<6>; +def TypeSYSTEM : Type<7>; +def TypeXTYPE : Type<8>; +def TypeMARKER : Type<31>; //===----------------------------------------------------------------------===// // Intruction Class Declaration + //===----------------------------------------------------------------------===// class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr, InstrItinClass itin> : Instruction { + string cstr, InstrItinClass itin, Type type> : Instruction { field bits<32> Inst; let Namespace = "Hexagon"; @@ -31,11 +44,15 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, let Constraints = cstr; let Itinerary = itin; - // *** The code below must match HexagonBaseInfo.h *** + // *** Must match HexagonBaseInfo.h *** + Type HexagonType = type; + let TSFlags{4-0} = HexagonType.Value; + bits<1> isHexagonSolo = 0; + let TSFlags{5} = isHexagonSolo; // Predicated instructions. bits<1> isPredicated = 0; - let TSFlags{1} = isPredicated; + let TSFlags{6} = isPredicated; // *** The code above must match HexagonBaseInfo.h *** } @@ -47,17 +64,25 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", LD> { + : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> { + bits<5> rd; + bits<5> rs; + bits<13> imm13; +} + +class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> { bits<5> rd; bits<5> rs; bits<13> imm13; + let mayLoad = 1; } // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> - : InstHexagon<outs, ins, asmstr, pattern, cstr, LD> { + : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -68,7 +93,24 @@ class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, // ST Instruction Class in V4 can take SLOT0 & SLOT1. // Definition of the instruction class CHANGED from V2/V3 to V4. class STInst<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", ST> { + : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> { + bits<5> rd; + bits<5> rs; + bits<13> imm13; +} + +class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> { + bits<5> rd; + bits<5> rs; + bits<13> imm13; + let mayStore = 1; +} + +// SYSTEM Instruction Class in V4 can take SLOT0 only +// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. +class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> { bits<5> rd; bits<5> rs; bits<13> imm13; @@ -79,7 +121,7 @@ class STInst<dag outs, dag ins, string asmstr, list<dag> pattern> // Definition of the instruction class CHANGED from V2/V3 to V4. class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ST> { + : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -89,7 +131,7 @@ class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, // ALU32 Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", ALU32> { + : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -102,7 +144,17 @@ class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern> // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", ALU64> { + : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> { + bits<5> rd; + bits<5> rs; + bits<5> rt; + bits<16> imm16; + bits<16> imm16_2; +} + +class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern, + string cstr> + : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -115,7 +167,7 @@ class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern> // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", M> { + : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -126,8 +178,8 @@ class MInst<dag outs, dag ins, string asmstr, list<dag> pattern> // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr> - : InstHexagon<outs, ins, asmstr, pattern, cstr, M> { + string cstr> + : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -138,9 +190,7 @@ class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst<dag outs, dag ins, string asmstr, list<dag> pattern> -//: InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, M)> { - : InstHexagon<outs, ins, asmstr, pattern, "", S> { -// : InstHexagon<outs, ins, asmstr, pattern, "", S> { + : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -151,8 +201,8 @@ class SInst<dag outs, dag ins, string asmstr, list<dag> pattern> // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr> - : InstHexagon<outs, ins, asmstr, pattern, cstr, S> { + string cstr> + : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> { // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> { // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> { bits<5> rd; @@ -163,14 +213,14 @@ class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, // J Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class JType<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", J> { + : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> { bits<16> imm16; } // JR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class JRType<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", JR> { + : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> { bits<5> rs; bits<5> pu; // Predicate register } @@ -178,15 +228,22 @@ class JRType<dag outs, dag ins, string asmstr, list<dag> pattern> // CR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", CR> { + : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> { bits<5> rs; bits<10> imm10; } +class Marker<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> { + let isCodeGenOnly = 1; + let isPseudo = 1; +} class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>; - + : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> { + let isCodeGenOnly = 1; + let isPseudo = 1; +} //===----------------------------------------------------------------------===// // Intruction Classes Definitions - @@ -222,6 +279,11 @@ class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern> : ALU64Type<outs, ins, asmstr, pattern> { } +class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern> + : ALU64Type<outs, ins, asmstr, pattern> { + let rt{0-4} = 0; +} + // J Type Instructions. class JInst<dag outs, dag ins, string asmstr, list<dag> pattern> : JType<outs, ins, asmstr, pattern> { @@ -239,12 +301,27 @@ class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> let rt{0-4} = 0; } +class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> + : STInstPost<outs, ins, asmstr, pattern, cstr> { + let rt{0-4} = 0; + let mayStore = 1; +} + + + // Post increment LD Instruction. class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> : LDInstPost<outs, ins, asmstr, pattern, cstr> { let rt{0-4} = 0; } +class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> + : LDInstPost<outs, ins, asmstr, pattern, cstr> { + let rt{0-4} = 0; + let mayLoad = 1; +} + + //===----------------------------------------------------------------------===// // V4 Instruction Format Definitions + //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/lib/Target/Hexagon/HexagonInstrFormatsV4.td index bd5e4493d7..49741a3d1b 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV4.td @@ -11,11 +11,25 @@ // //===----------------------------------------------------------------------===// +//----------------------------------------------------------------------------// +// Hexagon Intruction Flags + +// +// *** Must match BaseInfo.h *** +//----------------------------------------------------------------------------// + +def TypeMEMOP : Type<9>; +def TypeNV : Type<10>; +def TypePREFIX : Type<30>; + +//----------------------------------------------------------------------------// +// Intruction Classes Definitions + +//----------------------------------------------------------------------------// + // // NV type instructions. // class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", NV_V4> { + : InstHexagon<outs, ins, asmstr, pattern, "", NV_V4, TypeNV> { bits<5> rd; bits<5> rs; bits<13> imm13; @@ -24,7 +38,7 @@ class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern> // Definition of Post increment new value store. class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr> - : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4> { + : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV> { bits<5> rd; bits<5> rs; bits<5> rt; @@ -39,8 +53,15 @@ class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern, } class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4> { + : InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4, TypeMEMOP> { bits<5> rd; bits<5> rs; bits<6> imm6; } + +class Immext<dag outs, dag ins, string asmstr, list<dag> pattern> + : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX> { + let isCodeGenOnly = 1; + + bits<26> imm26; +} diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index a3918692db..bbb3323223 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -11,10 +11,10 @@ // //===----------------------------------------------------------------------===// -#include "Hexagon.h" #include "HexagonInstrInfo.h" #include "HexagonRegisterInfo.h" #include "HexagonSubtarget.h" +#include "Hexagon.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/DFAPacketizer.h" @@ -34,23 +34,23 @@ using namespace llvm; /// Constants for Hexagon instructions. /// const int Hexagon_MEMW_OFFSET_MAX = 4095; -const int Hexagon_MEMW_OFFSET_MIN = 4096; +const int Hexagon_MEMW_OFFSET_MIN = -4096; const int Hexagon_MEMD_OFFSET_MAX = 8191; -const int Hexagon_MEMD_OFFSET_MIN = 8192; +const int Hexagon_MEMD_OFFSET_MIN = -8192; const int Hexagon_MEMH_OFFSET_MAX = 2047; -const int Hexagon_MEMH_OFFSET_MIN = 2048; +const int Hexagon_MEMH_OFFSET_MIN = -2048; const int Hexagon_MEMB_OFFSET_MAX = 1023; -const int Hexagon_MEMB_OFFSET_MIN = 1024; +const int Hexagon_MEMB_OFFSET_MIN = -1024; const int Hexagon_ADDI_OFFSET_MAX = 32767; -const int Hexagon_ADDI_OFFSET_MIN = 32768; +const int Hexagon_ADDI_OFFSET_MIN = -32768; const int Hexagon_MEMD_AUTOINC_MAX = 56; -const int Hexagon_MEMD_AUTOINC_MIN = 64; +const int Hexagon_MEMD_AUTOINC_MIN = -64; const int Hexagon_MEMW_AUTOINC_MAX = 28; -const int Hexagon_MEMW_AUTOINC_MIN = 32; +const int Hexagon_MEMW_AUTOINC_MIN = -32; const int Hexagon_MEMH_AUTOINC_MAX = 14; -const int Hexagon_MEMH_AUTOINC_MIN = 16; +const int Hexagon_MEMH_AUTOINC_MIN = -16; const int Hexagon_MEMB_AUTOINC_MAX = 7; -const int Hexagon_MEMB_AUTOINC_MIN = 8; +const int Hexagon_MEMB_AUTOINC_MIN = -8; @@ -70,6 +70,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, switch (MI->getOpcode()) { + default: break; case Hexagon::LDriw: case Hexagon::LDrid: case Hexagon::LDrih: @@ -81,11 +82,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, return MI->getOperand(0).getReg(); } break; - - default: - break; } - return 0; } @@ -98,6 +95,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { + default: break; case Hexagon::STriw: case Hexagon::STrid: case Hexagon::STrih: @@ -108,11 +106,7 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, return MI->getOperand(0).getReg(); } break; - - default: - break; } - return 0; } @@ -415,7 +409,6 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align); - if (RC == &Hexagon::IntRegsRegClass) { BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); @@ -452,20 +445,860 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *TRC; - if (VT == MVT::i1) + if (VT == MVT::i1) { TRC = &Hexagon::PredRegsRegClass; - else if (VT == MVT::i32) + } else if (VT == MVT::i32 || VT == MVT::f32) { TRC = &Hexagon::IntRegsRegClass; - else if (VT == MVT::i64) + } else if (VT == MVT::i64 || VT == MVT::f64) { TRC = &Hexagon::DoubleRegsRegClass; - else + } else { llvm_unreachable("Cannot handle this register class"); + } unsigned NewReg = RegInfo.createVirtualRegister(TRC); return NewReg; } +bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { + switch(MI->getOpcode()) { + default: return false; + // JMP_EQri + case Hexagon::JMP_EQriPt_nv_V4: + case Hexagon::JMP_EQriPnt_nv_V4: + case Hexagon::JMP_EQriNotPt_nv_V4: + case Hexagon::JMP_EQriNotPnt_nv_V4: + + // JMP_EQri - with -1 + case Hexagon::JMP_EQriPtneg_nv_V4: + case Hexagon::JMP_EQriPntneg_nv_V4: + case Hexagon::JMP_EQriNotPtneg_nv_V4: + case Hexagon::JMP_EQriNotPntneg_nv_V4: + + // JMP_EQrr + case Hexagon::JMP_EQrrPt_nv_V4: + case Hexagon::JMP_EQrrPnt_nv_V4: + case Hexagon::JMP_EQrrNotPt_nv_V4: + case Hexagon::JMP_EQrrNotPnt_nv_V4: + + // JMP_GTri + case Hexagon::JMP_GTriPt_nv_V4: + case Hexagon::JMP_GTriPnt_nv_V4: + case Hexagon::JMP_GTriNotPt_nv_V4: + case Hexagon::JMP_GTriNotPnt_nv_V4: + + // JMP_GTri - with -1 + case Hexagon::JMP_GTriPtneg_nv_V4: + case Hexagon::JMP_GTriPntneg_nv_V4: + case Hexagon::JMP_GTriNotPtneg_nv_V4: + case Hexagon::JMP_GTriNotPntneg_nv_V4: + + // JMP_GTrr + case Hexagon::JMP_GTrrPt_nv_V4: + case Hexagon::JMP_GTrrPnt_nv_V4: + case Hexagon::JMP_GTrrNotPt_nv_V4: + case Hexagon::JMP_GTrrNotPnt_nv_V4: + + // JMP_GTrrdn + case Hexagon::JMP_GTrrdnPt_nv_V4: + case Hexagon::JMP_GTrrdnPnt_nv_V4: + case Hexagon::JMP_GTrrdnNotPt_nv_V4: + case Hexagon::JMP_GTrrdnNotPnt_nv_V4: + + // JMP_GTUri + case Hexagon::JMP_GTUriPt_nv_V4: + case Hexagon::JMP_GTUriPnt_nv_V4: + case Hexagon::JMP_GTUriNotPt_nv_V4: + case Hexagon::JMP_GTUriNotPnt_nv_V4: + + // JMP_GTUrr + case Hexagon::JMP_GTUrrPt_nv_V4: + case Hexagon::JMP_GTUrrPnt_nv_V4: + case Hexagon::JMP_GTUrrNotPt_nv_V4: + case Hexagon::JMP_GTUrrNotPnt_nv_V4: + + // JMP_GTUrrdn + case Hexagon::JMP_GTUrrdnPt_nv_V4: + case Hexagon::JMP_GTUrrdnPnt_nv_V4: + case Hexagon::JMP_GTUrrdnNotPt_nv_V4: + case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: + + // TFR_FI + case Hexagon::TFR_FI: + return true; + } +} + +bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { + switch(MI->getOpcode()) { + default: return false; + // JMP_EQri + case Hexagon::JMP_EQriPt_ie_nv_V4: + case Hexagon::JMP_EQriPnt_ie_nv_V4: + case Hexagon::JMP_EQriNotPt_ie_nv_V4: + case Hexagon::JMP_EQriNotPnt_ie_nv_V4: + + // JMP_EQri - with -1 + case Hexagon::JMP_EQriPtneg_ie_nv_V4: + case Hexagon::JMP_EQriPntneg_ie_nv_V4: + case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: + case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: + + // JMP_EQrr + case Hexagon::JMP_EQrrPt_ie_nv_V4: + case Hexagon::JMP_EQrrPnt_ie_nv_V4: + case Hexagon::JMP_EQrrNotPt_ie_nv_V4: + case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: + + // JMP_GTri + case Hexagon::JMP_GTriPt_ie_nv_V4: + case Hexagon::JMP_GTriPnt_ie_nv_V4: + case Hexagon::JMP_GTriNotPt_ie_nv_V4: + case Hexagon::JMP_GTriNotPnt_ie_nv_V4: + + // JMP_GTri - with -1 + case Hexagon::JMP_GTriPtneg_ie_nv_V4: + case Hexagon::JMP_GTriPntneg_ie_nv_V4: + case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: + case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: + + // JMP_GTrr + case Hexagon::JMP_GTrrPt_ie_nv_V4: + case Hexagon::JMP_GTrrPnt_ie_nv_V4: + case Hexagon::JMP_GTrrNotPt_ie_nv_V4: + case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: + + // JMP_GTrrdn + case Hexagon::JMP_GTrrdnPt_ie_nv_V4: + case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: + case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: + case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: + + // JMP_GTUri + case Hexagon::JMP_GTUriPt_ie_nv_V4: + case Hexagon::JMP_GTUriPnt_ie_nv_V4: + case Hexagon::JMP_GTUriNotPt_ie_nv_V4: + case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: + + // JMP_GTUrr + case Hexagon::JMP_GTUrrPt_ie_nv_V4: + case Hexagon::JMP_GTUrrPnt_ie_nv_V4: + case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: + case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: + + // JMP_GTUrrdn + case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: + + // V4 absolute set addressing. + case Hexagon::LDrid_abs_setimm_V4: + case Hexagon::LDriw_abs_setimm_V4: + case Hexagon::LDrih_abs_setimm_V4: + case Hexagon::LDrib_abs_setimm_V4: + case Hexagon::LDriuh_abs_setimm_V4: + case Hexagon::LDriub_abs_setimm_V4: + + case Hexagon::STrid_abs_setimm_V4: + case Hexagon::STrib_abs_setimm_V4: + case Hexagon::STrih_abs_setimm_V4: + case Hexagon::STriw_abs_setimm_V4: + + // V4 global address load. + case Hexagon::LDrid_GP_cPt_V4 : + case Hexagon::LDrid_GP_cNotPt_V4 : + case Hexagon::LDrid_GP_cdnPt_V4 : + case Hexagon::LDrid_GP_cdnNotPt_V4 : + case Hexagon::LDrib_GP_cPt_V4 : + case Hexagon::LDrib_GP_cNotPt_V4 : + case Hexagon::LDrib_GP_cdnPt_V4 : + case Hexagon::LDrib_GP_cdnNotPt_V4 : + case Hexagon::LDriub_GP_cPt_V4 : + case Hexagon::LDriub_GP_cNotPt_V4 : + case Hexagon::LDriub_GP_cdnPt_V4 : + case Hexagon::LDriub_GP_cdnNotPt_V4 : + case Hexagon::LDrih_GP_cPt_V4 : + case Hexagon::LDrih_GP_cNotPt_V4 : + case Hexagon::LDrih_GP_cdnPt_V4 : + case Hexagon::LDrih_GP_cdnNotPt_V4 : + case Hexagon::LDriuh_GP_cPt_V4 : + case Hexagon::LDriuh_GP_cNotPt_V4 : + case Hexagon::LDriuh_GP_cdnPt_V4 : + case Hexagon::LDriuh_GP_cdnNotPt_V4 : + case Hexagon::LDriw_GP_cPt_V4 : + case Hexagon::LDriw_GP_cNotPt_V4 : + case Hexagon::LDriw_GP_cdnPt_V4 : + case Hexagon::LDriw_GP_cdnNotPt_V4 : + case Hexagon::LDd_GP_cPt_V4 : + case Hexagon::LDd_GP_cNotPt_V4 : + case Hexagon::LDd_GP_cdnPt_V4 : + case Hexagon::LDd_GP_cdnNotPt_V4 : + case Hexagon::LDb_GP_cPt_V4 : + case Hexagon::LDb_GP_cNotPt_V4 : + case Hexagon::LDb_GP_cdnPt_V4 : + case Hexagon::LDb_GP_cdnNotPt_V4 : + case Hexagon::LDub_GP_cPt_V4 : + case Hexagon::LDub_GP_cNotPt_V4 : + case Hexagon::LDub_GP_cdnPt_V4 : + case Hexagon::LDub_GP_cdnNotPt_V4 : + case Hexagon::LDh_GP_cPt_V4 : + case Hexagon::LDh_GP_cNotPt_V4 : + case Hexagon::LDh_GP_cdnPt_V4 : + case Hexagon::LDh_GP_cdnNotPt_V4 : + case Hexagon::LDuh_GP_cPt_V4 : + case Hexagon::LDuh_GP_cNotPt_V4 : + case Hexagon::LDuh_GP_cdnPt_V4 : + case Hexagon::LDuh_GP_cdnNotPt_V4 : + case Hexagon::LDw_GP_cPt_V4 : + case Hexagon::LDw_GP_cNotPt_V4 : + case Hexagon::LDw_GP_cdnPt_V4 : + case Hexagon::LDw_GP_cdnNotPt_V4 : + + // V4 global address store. + case Hexagon::STrid_GP_cPt_V4 : + case Hexagon::STrid_GP_cNotPt_V4 : + case Hexagon::STrid_GP_cdnPt_V4 : + case Hexagon::STrid_GP_cdnNotPt_V4 : + case Hexagon::STrib_GP_cPt_V4 : + case Hexagon::STrib_GP_cNotPt_V4 : + case Hexagon::STrib_GP_cdnPt_V4 : + case Hexagon::STrib_GP_cdnNotPt_V4 : + case Hexagon::STrih_GP_cPt_V4 : + case Hexagon::STrih_GP_cNotPt_V4 : + case Hexagon::STrih_GP_cdnPt_V4 : + case Hexagon::STrih_GP_cdnNotPt_V4 : + case Hexagon::STriw_GP_cPt_V4 : + case Hexagon::STriw_GP_cNotPt_V4 : + case Hexagon::STriw_GP_cdnPt_V4 : + case Hexagon::STriw_GP_cdnNotPt_V4 : + case Hexagon::STd_GP_cPt_V4 : + case Hexagon::STd_GP_cNotPt_V4 : + case Hexagon::STd_GP_cdnPt_V4 : + case Hexagon::STd_GP_cdnNotPt_V4 : + case Hexagon::STb_GP_cPt_V4 : + case Hexagon::STb_GP_cNotPt_V4 : + case Hexagon::STb_GP_cdnPt_V4 : + case Hexagon::STb_GP_cdnNotPt_V4 : + case Hexagon::STh_GP_cPt_V4 : + case Hexagon::STh_GP_cNotPt_V4 : + case Hexagon::STh_GP_cdnPt_V4 : + case Hexagon::STh_GP_cdnNotPt_V4 : + case Hexagon::STw_GP_cPt_V4 : + case Hexagon::STw_GP_cNotPt_V4 : + case Hexagon::STw_GP_cdnPt_V4 : + case Hexagon::STw_GP_cdnNotPt_V4 : + + // V4 predicated global address new value store. + case Hexagon::STrib_GP_cPt_nv_V4 : + case Hexagon::STrib_GP_cNotPt_nv_V4 : + case Hexagon::STrib_GP_cdnPt_nv_V4 : + case Hexagon::STrib_GP_cdnNotPt_nv_V4 : + case Hexagon::STrih_GP_cPt_nv_V4 : + case Hexagon::STrih_GP_cNotPt_nv_V4 : + case Hexagon::STrih_GP_cdnPt_nv_V4 : + case Hexagon::STrih_GP_cdnNotPt_nv_V4 : + case Hexagon::STriw_GP_cPt_nv_V4 : + case Hexagon::STriw_GP_cNotPt_nv_V4 : + case Hexagon::STriw_GP_cdnPt_nv_V4 : + case Hexagon::STriw_GP_cdnNotPt_nv_V4 : + case Hexagon::STb_GP_cPt_nv_V4 : + case Hexagon::STb_GP_cNotPt_nv_V4 : + case Hexagon::STb_GP_cdnPt_nv_V4 : + case Hexagon::STb_GP_cdnNotPt_nv_V4 : + case Hexagon::STh_GP_cPt_nv_V4 : + case Hexagon::STh_GP_cNotPt_nv_V4 : + case Hexagon::STh_GP_cdnPt_nv_V4 : + case Hexagon::STh_GP_cdnNotPt_nv_V4 : + case Hexagon::STw_GP_cPt_nv_V4 : + case Hexagon::STw_GP_cNotPt_nv_V4 : + case Hexagon::STw_GP_cdnPt_nv_V4 : + case Hexagon::STw_GP_cdnNotPt_nv_V4 : + + // TFR_FI + case Hexagon::TFR_FI_immext_V4: + return true; + } +} + +bool |