diff options
| -rw-r--r-- | lib/CodeGen/MachineScheduler.cpp | 2 | ||||
| -rw-r--r-- | lib/CodeGen/RegisterPressure.cpp | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index 41b4b719f2..1d810fdf16 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -819,8 +819,6 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) { assert(TopQueue.empty() && BotQueue.empty() && "ReadyQ garbage"); return NULL; } - // As an initial placeholder heuristic, schedule in the direction that has - // the fewest choices. SUnit *SU; if (ForceTopDown) { SU = DAG->getSUnit(DAG->top()); diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp index fbd08cb575..912ed0dd7b 100644 --- a/lib/CodeGen/RegisterPressure.cpp +++ b/lib/CodeGen/RegisterPressure.cpp @@ -698,7 +698,7 @@ getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta) { unsigned Reg = VirtRegOpers.Uses[i]; const LiveInterval *LI = &LIS->getInterval(Reg); // FIXME: allow the caller to pass in the list of vreg uses that remain to - // be top-scheduled to avoid searching uses at each query. + // be bottom-scheduled to avoid searching uses at each query. SlotIndex CurrIdx = LIS->getInstructionIndex(CurrPos).getRegSlot(); if (LI->killedAt(SlotIdx) && !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) { |