make tblgen produce a function that returns the name for a physreg.

Nothing is using this info yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81707 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 49 insertions, 8 deletions

diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
index a6f614958b..0455c9b5e8 100644
--- a/utils/TableGen/AsmWriterEmitter.cpp
+++ b/utils/TableGen/AsmWriterEmitter.cpp
@@ -538,19 +538,16 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
 }
 
 
-
-void AsmWriterEmitter::run(raw_ostream &O) {
-  EmitSourceFileHeader("Assembly Writer Source Fragment", O);
-
+/// EmitPrintInstruction - Generate the code for the "printInstruction" method
+/// implementation.
+void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
   CodeGenTarget Target;
   Record *AsmWriter = Target.getAsmWriter();
   std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
-
+  
   O <<
   "/// printInstruction - This method is automatically generated by tablegen\n"
-  "/// from the instruction set description.  This method returns true if the\n"
-  "/// machine instruction was sufficiently described to print it, otherwise\n"
-  "/// it returns false.\n"
+  "/// from the instruction set description.\n"
     "void " << Target.getName() << ClassName
             << "::printInstruction(const MachineInstr *MI) {\n";
 
@@ -794,3 +791,44 @@ void AsmWriterEmitter::run(raw_ostream &O) {
   O << "  return;\n";
   O << "}\n";
 }
+
+
+void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
+  CodeGenTarget Target;
+  Record *AsmWriter = Target.getAsmWriter();
+  std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+  const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
+  
+  O <<
+  "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
+  "/// from the register set description.  This returns the assembler name\n"
+  "/// for the specified register.\n"
+  "const char *" << Target.getName() << ClassName
+  << "::getRegisterName(unsigned RegNo) const {\n"
+  << "  assert(RegNo && RegNo < " << (Registers.size()+1)
+  << " && \"Invalid register number!\");\n"
+  << "\n"
+  << "  static const char *const RegAsmNames[] = {\n";
+  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
+    const CodeGenRegister &Reg = Registers[i];
+
+    std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
+    if (AsmName.empty())
+      AsmName = Reg.getName();
+    O << "    \"" << AsmName << "\",\n";
+  }
+  O << "    0\n"
+    << "  };\n"
+    << "\n"
+    << "  return RegAsmNames[RegNo-1];\n"
+    << "}\n";
+}
+
+
+void AsmWriterEmitter::run(raw_ostream &O) {
+  EmitSourceFileHeader("Assembly Writer Source Fragment", O);
+  
+  EmitPrintInstruction(O);
+  EmitGetRegisterName(O);
+}
+
diff --git a/utils/TableGen/AsmWriterEmitter.h b/utils/TableGen/AsmWriterEmitter.h
index 75e69964ef..7862caa25a 100644
--- a/utils/TableGen/AsmWriterEmitter.h
+++ b/utils/TableGen/AsmWriterEmitter.h
@@ -35,6 +35,9 @@ namespace llvm {
     void run(raw_ostream &o);
 
 private:
+    void EmitPrintInstruction(raw_ostream &o);
+    void EmitGetRegisterName(raw_ostream &o);
+    
     AsmWriterInst *getAsmWriterInstByID(unsigned ID) const {
       assert(ID < NumberedInstructions.size());
       std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I =