diff options
| author | Dan Gohman <gohman@apple.com> | 2011-10-25 00:05:42 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2011-10-25 00:05:42 +0000 |
| commit | 3e6157de576e349d33a9b08d103405b3a8fb9159 (patch) | |
| tree | e052c80458eed89e821b001205b9401a66b754bc /utils/lit | |
| parent | 29074ccf6cb00a3cbe32a3b7809d970ecaf8c9bf (diff) | |
Remove the Blackfin backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142880 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/lit')
| -rw-r--r-- | utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp | 2 | ||||
| -rw-r--r-- | utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp b/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp index 63ae88d1f0..3d63966b7f 100644 --- a/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp +++ b/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp @@ -2,7 +2,7 @@ # Do not edit here. If you wish to override these values # edit the last section set target_triplet "x86_64-apple-darwin10" -set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend" +set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend" set llvmgcc_langs "c,c++,objc,obj-c++" set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl" set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin" diff --git a/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp b/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp index 63ae88d1f0..3d63966b7f 100644 --- a/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp +++ b/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp @@ -2,7 +2,7 @@ # Do not edit here. If you wish to override these values # edit the last section set target_triplet "x86_64-apple-darwin10" -set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend" +set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend" set llvmgcc_langs "c,c++,objc,obj-c++" set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl" set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin" |