diff options
| author | Craig Topper <craig.topper@gmail.com> | 2011-11-06 23:04:08 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-11-06 23:04:08 +0000 |
| commit | c8eb880a7fb0958a3a048a82c8558beec11f1209 (patch) | |
| tree | b78bcb93cbee0801c40e6176ccc83d25b62dd637 /utils/TableGen | |
| parent | 590853667345d6fb191764b9d0bd2ff13589e3a3 (diff) | |
More AVX2 instructions and their intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
| -rw-r--r-- | utils/TableGen/X86DisassemblerTables.cpp | 7 | ||||
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 9 |
2 files changed, 12 insertions, 4 deletions
diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp index e8c9a48973..61e94521f5 100644 --- a/utils/TableGen/X86DisassemblerTables.cpp +++ b/utils/TableGen/X86DisassemblerTables.cpp @@ -95,7 +95,10 @@ static inline bool inheritsFrom(InstructionContext child, case IC_VEX_L: case IC_VEX_L_XS: case IC_VEX_L_XD: + return false; case IC_VEX_L_OPSIZE: + return inheritsFrom(child, IC_VEX_L_W_OPSIZE); + case IC_VEX_L_W_OPSIZE: return false; default: llvm_unreachable("Unknown instruction class"); @@ -494,7 +497,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const { for (index = 0; index < 256; ++index) { o.indent(i * 2); - if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) + if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) + o << "IC_VEX_L_W_OPSIZE"; + else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) o << "IC_VEX_L_OPSIZE"; else if ((index & ATTR_VEXL) && (index & ATTR_XD)) o << "IC_VEX_L_XD"; diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index d4c9629226..3478809c7a 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -285,9 +285,12 @@ InstructionContext RecognizableInstr::insnContext() const { InstructionContext insnContext; if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) { - if (HasVEX_LPrefix && HasVEX_WPrefix) - llvm_unreachable("Don't support VEX.L and VEX.W together"); - else if (HasOpSizePrefix && HasVEX_LPrefix) + if (HasVEX_LPrefix && HasVEX_WPrefix) { + if (HasOpSizePrefix) + insnContext = IC_VEX_L_W_OPSIZE; + else + llvm_unreachable("Don't support VEX.L and VEX.W together"); + } else if (HasOpSizePrefix && HasVEX_LPrefix) insnContext = IC_VEX_L_OPSIZE; else if (HasOpSizePrefix && HasVEX_WPrefix) insnContext = IC_VEX_W_OPSIZE; |