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| author | Richard Barton <richard.barton@arm.com> | 2012-04-27 17:34:01 +0000 |
|---|---|---|
| committer | Richard Barton <richard.barton@arm.com> | 2012-04-27 17:34:01 +0000 |
| commit | 04a09a461beb4ec629fe53e601b7665547ac35c3 (patch) | |
| tree | 2f652e32aa51959f22e42daf908e565a5ac5e1ec /test | |
| parent | a4c4df429454ba701f21b0bcfd05735729e718f3 (diff) | |
Fix ARM assembly parsing for upper case condition codes on IT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 68ef2897c1..4aed9e2bea 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -509,6 +509,19 @@ _func: @ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b] @ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] +@ Should also work for UPPER CASE condition codes. + + ITEET EQ + ADDEQ R0, R1, R2 + NOPNE + SUBNE R5, R6, R7 + ADDEQ R1, R2, #4 + +@ CHECK: iteet eq @ encoding: [0x0d,0xbf] +@ CHECK: addeq r0, r1, r2 @ encoding: [0x88,0x18] +@ CHECK: nopne @ encoding: [0x00,0xbf] +@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b] +@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] @------------------------------------------------------------------------------ @ LDC{L}/LDC2{L} |