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| author | Eli Bendersky <eliben@chromium.org> | 2013-07-15 16:09:15 -0700 |
|---|---|---|
| committer | Eli Bendersky <eliben@chromium.org> | 2013-07-15 16:09:15 -0700 |
| commit | c6cf05cb5108f356dde97c01ee4188b0671d4542 (patch) | |
| tree | 436fdc2a55296d3c202e7ef11f31be3be53efb5f /test/Transforms/LoopVectorize/bsd_regex.ll | |
| parent | c75199c649c739aade160289d93f257edc798cde (diff) | |
| parent | 7dfcb84fc16b3bf6b2379713b53090757f0a45f9 (diff) | |
Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'
Conflicts:
docs/LangRef.rst
include/llvm/CodeGen/CallingConvLower.h
include/llvm/IRReader/IRReader.h
include/llvm/Target/TargetMachine.h
lib/CodeGen/CallingConvLower.cpp
lib/IRReader/IRReader.cpp
lib/IRReader/LLVMBuild.txt
lib/IRReader/Makefile
lib/LLVMBuild.txt
lib/Makefile
lib/Support/MemoryBuffer.cpp
lib/Support/Unix/PathV2.inc
lib/Target/ARM/ARMBaseInstrInfo.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMInstrInfo.td
lib/Target/ARM/ARMSubtarget.cpp
lib/Target/ARM/ARMTargetMachine.cpp
lib/Target/Mips/CMakeLists.txt
lib/Target/Mips/MipsDelaySlotFiller.cpp
lib/Target/Mips/MipsISelLowering.cpp
lib/Target/Mips/MipsInstrInfo.td
lib/Target/Mips/MipsSubtarget.cpp
lib/Target/Mips/MipsSubtarget.h
lib/Target/X86/X86FastISel.cpp
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrControl.td
lib/Target/X86/X86InstrFormats.td
lib/Transforms/IPO/ExtractGV.cpp
lib/Transforms/InstCombine/InstCombineCompares.cpp
lib/Transforms/Utils/SimplifyLibCalls.cpp
test/CodeGen/X86/fast-isel-divrem.ll
test/MC/ARM/data-in-code.ll
tools/Makefile
tools/llvm-extract/llvm-extract.cpp
tools/llvm-link/CMakeLists.txt
tools/opt/CMakeLists.txt
tools/opt/LLVMBuild.txt
tools/opt/Makefile
tools/opt/opt.cpp
Diffstat (limited to 'test/Transforms/LoopVectorize/bsd_regex.ll')
| -rw-r--r-- | test/Transforms/LoopVectorize/bsd_regex.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/test/Transforms/LoopVectorize/bsd_regex.ll b/test/Transforms/LoopVectorize/bsd_regex.ll new file mode 100644 index 0000000000..a14b92d229 --- /dev/null +++ b/test/Transforms/LoopVectorize/bsd_regex.ll @@ -0,0 +1,38 @@ +; RUN: opt -S -loop-vectorize -dce -instcombine -force-vector-width=2 -force-vector-unroll=2 < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +;PR 15830. + +;CHECK: foo +; When scalarizing stores we need to preserve the original order. +; Make sure that we are extracting in the correct order (0101, and not 0011). +;CHECK: extractelement <2 x i64> {{.*}}, i32 0 +;CHECK: extractelement <2 x i64> {{.*}}, i32 1 +;CHECK: extractelement <2 x i64> {{.*}}, i32 0 +;CHECK: extractelement <2 x i64> {{.*}}, i32 1 +;CHECK: store +;CHECK: store +;CHECK: store +;CHECK: store +;CHECK: ret + +define i32 @foo(i32* nocapture %A) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %0 = shl nsw i64 %indvars.iv, 2 + %arrayidx = getelementptr inbounds i32* %A, i64 %0 + store i32 4, i32* %arrayidx, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 10000 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 undef +} + + |