Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121584 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 10 insertions, 25 deletions

diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp
index 3f08439fac..26d4cd4d75 100644
--- a/lib/CodeGen/AllocationOrder.cpp
+++ b/lib/CodeGen/AllocationOrder.cpp
@@ -36,6 +36,10 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
   if (Hint && TargetRegisterInfo::isVirtualRegister(Hint))
     Hint = VRM.getPhys(Hint);
 
+  // The remaining allocation order may depend on the hint.
+  tie(Begin, End) = VRM.getTargetRegInfo()
+        .getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
+
   // Target-dependent hints require resolution.
   if (HintPair.first)
     Hint = VRM.getTargetRegInfo().ResolveRegAllocHint(HintPair.first, Hint,
@@ -45,10 +49,6 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
   if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
                !RC->contains(Hint) || ReservedRegs.test(Hint)))
     Hint = 0;
-
-  // The remaining allocation order may also depend on the hint.
-  tie(Begin, End) = VRM.getTargetRegInfo()
-        .getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
 }
 
 unsigned AllocationOrder::next() {
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index ecdc419355..df816f6539 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "regalloc"
+#include "AllocationOrder.h"
 #include "LiveIntervalUnion.h"
 #include "RegAllocBase.h"
 #include "Spiller.h"
@@ -175,12 +176,9 @@ bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
   assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
          "inconsistent phys reg assigment");
 
-  const TargetRegisterClass *TRC = MRI->getRegClass(InterferingVReg.reg);
-  for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
-         E = TRC->allocation_order_end(*MF);
-       I != E; ++I) {
-    unsigned PhysReg = *I;
-    if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg))
+  AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
+  while (unsigned PhysReg = Order.next()) {
+    if (PhysReg == OldPhysReg)
       continue;
 
     if (checkUncachedInterference(InterferingVReg, PhysReg))
@@ -235,21 +233,8 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
   const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
   DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
 
-  // Preferred physical register computed from hints.
-  unsigned Hint = VRM->getRegAllocPref(VirtReg.reg);
-
-  // Try a hinted allocation.
-  if (Hint && !ReservedRegs.test(Hint) && TRC->contains(Hint) &&
-      checkPhysRegInterference(VirtReg, Hint) == 0)
-    return Hint;
-
-  for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
-         E = TRC->allocation_order_end(*MF);
-       I != E; ++I) {
-
-    unsigned PhysReg = *I;
-    if (ReservedRegs.test(PhysReg)) continue;
-
+  AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
+  while (unsigned PhysReg = Order.next()) {
     // Check interference and as a side effect, intialize queries for this
     // VirtReg and its aliases.
     unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg);