diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2009-07-25 01:55:25 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-25 01:55:25 +0000 |
| commit | c7423aff68630d7fd1250337505a8e4be09d0f15 (patch) | |
| tree | a5d1c01d47df76854e4862f980f1199ca9922a37 /lib | |
| parent | fd87a544c00c2ca04ee23aae67bbcad4dc852a54 (diff) | |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 6b0692c763..2405bd03fd 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -959,7 +959,8 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB, assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); // Build the new ADD / SUB. - BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg) + unsigned Opc = TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri); + BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) .addReg(BaseReg, RegState::Kill).addImm(ThisVal) .addImm((unsigned)Pred).addReg(PredReg).addReg(0); BaseReg = DestReg; |