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| author | Chad Rosier <mcrosier@apple.com> | 2011-12-21 19:14:52 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-12-21 19:14:52 +0000 |
| commit | 649326ab15d7092ad12ceb592127a28d3d17d432 (patch) | |
| tree | 4cfa9b30f0e3d90e25f2ad35f64b71c7f2168d5f /lib | |
| parent | 8d0447c506eceddcebb1d4eb3bb869a83de19d84 (diff) | |
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
necessary. Please chime in if I'm mistaken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 95c99e1dc2..d8481b8091 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1190,7 +1190,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine(ISD::VECTOR_SHUFFLE); setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); - setTargetDAGCombine(ISD::BUILD_VECTOR); setTargetDAGCombine(ISD::VSELECT); setTargetDAGCombine(ISD::SELECT); setTargetDAGCombine(ISD::SHL); |