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authorBob Wilson <bob.wilson@apple.com>2009-10-06 20:18:46 +0000
committerBob Wilson <bob.wilson@apple.com>2009-10-06 20:18:46 +0000
commita3e8bf8412481139827b61f83bdd84637af800b8 (patch)
tree0d4f3c8eb4b1694e4dd6b919f74e2599c3728071 /lib
parent35b305863ad821004f27b97546597c5ba6a65172 (diff)
Fix a comment typo.
Patch by Johnny Chen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 9571ecd37a..da048be20c 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -384,7 +384,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
}
/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
-/// instruction modifies the CSPR register.
+/// instruction modifies the CPSR register.
let Defs = [CPSR] in {
multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> {