Add X86 RORX instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 36 insertions, 0 deletions

diff --git a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index 007e620cae..c50f785172 100644
--- a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -301,6 +301,9 @@ namespace X86II {
     // T8XS - Prefix before and after 0x0F. Combination of T8 and XS.
     T8XS = 18 << Op0Shift,
 
+    // TAXD - Prefix before and after 0x0F. Combination of TA and XD.
+    TAXD = 19 << Op0Shift,
+
     //===------------------------------------------------------------------===//
     // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
     // They are used to specify GPRs and SSE registers, 64-bit operand size,
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 8ae7a3c42a..1ab469cc00 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -472,6 +472,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
     VEX_PP = 0x3;
     VEX_5M = 0x2;
     break;
+  case X86II::TAXD: // F2 0F 3A
+    VEX_PP = 0x3;
+    VEX_5M = 0x3;
+    break;
   case X86II::XS:  // F3 0F
     VEX_PP = 0x2;
     break;
@@ -802,6 +806,10 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
     EmitByte(0xF2, CurByte, OS);
     Need0FPrefix = true;
     break;
+  case X86II::TAXD: // F2 0F 3A
+    EmitByte(0xF2, CurByte, OS);
+    Need0FPrefix = true;
+    break;
   case X86II::XS:   // F3 0F
     EmitByte(0xF3, CurByte, OS);
     Need0FPrefix = true;
@@ -838,6 +846,7 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
   case X86II::T8:    // 0F 38
     EmitByte(0x38, CurByte, OS);
     break;
+  case X86II::TAXD:  // F2 0F 3A
   case X86II::TA:    // 0F 3A
     EmitByte(0x3A, CurByte, OS);
     break;
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index a15060462e..d94ba331fb 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -656,6 +656,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
     Need0FPrefix = true;
     break;
   case X86II::T8XD: // F2 0F 38
+  case X86II::TAXD: // F2 0F 3A
   case X86II::XD:   // F2 0F
     MCE.emitByte(0xF2);
     Need0FPrefix = true;
@@ -686,6 +687,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
   case X86II::T8:    // 0F 38
     MCE.emitByte(0x38);
     break;
+  case X86II::TAXD:  // F2 0F 38
   case X86II::TA:    // 0F 3A
     MCE.emitByte(0x3A);
     break;
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td
index 5b7adf311b..5236dafd99 100644
--- a/lib/Target/X86/X86InstrFormats.td
+++ b/lib/Target/X86/X86InstrFormats.td
@@ -109,6 +109,7 @@ class A6     { bits<5> Prefix = 15; }
 class A7     { bits<5> Prefix = 16; }
 class T8XD   { bits<5> Prefix = 17; }
 class T8XS   { bits<5> Prefix = 18; }
+class TAXD   { bits<5> Prefix = 19; }
 class VEX    { bit hasVEXPrefix = 1; }
 class VEX_W  { bit hasVEX_WPrefix = 1; }
 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
diff --git a/lib/Target/X86/X86InstrShiftRotate.td b/lib/Target/X86/X86InstrShiftRotate.td
index 8278568184..a32f0665d3 100644
--- a/lib/Target/X86/X86InstrShiftRotate.td
+++ b/lib/Target/X86/X86InstrShiftRotate.td
@@ -744,3 +744,24 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
 
 } // Defs = [EFLAGS]
 
+let Predicates = [HasBMI2], neverHasSideEffects = 1 in {
+  def RORX32ri : Ii8<0xF0, MRMSrcReg, (outs GR32:$dst),
+                     (ins GR32:$src1, i8imm:$src2),
+                     "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                     TAXD, VEX;
+  let mayLoad = 1 in
+  def RORX32mi : Ii8<0xF0, MRMSrcMem, (outs GR32:$dst),
+                     (ins i32mem:$src1, i8imm:$src2),
+                     "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                     TAXD, VEX;
+
+  def RORX64ri : Ii8<0xF0, MRMSrcReg, (outs GR64:$dst),
+                     (ins GR64:$src1, i8imm:$src2),
+                     "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                     TAXD, VEX, VEX_W;
+  let mayLoad = 1 in
+  def RORX64mi : Ii8<0xF0, MRMSrcMem, (outs GR64:$dst),
+                     (ins i64mem:$src1, i8imm:$src2),
+                     "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                     TAXD, VEX, VEX_W;
+}