Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8

34 files changed, 253 insertions, 270 deletions

diff --git a/lib/Target/Mips/Makefile b/lib/Target/Mips/Makefile
index bf77bdbcdc..d16b066a62 100644
--- a/lib/Target/Mips/Makefile
+++ b/lib/Target/Mips/Makefile
@@ -1,11 +1,11 @@
-##===- lib/Target/Mips/Makefile ---------------------------*- Makefile -*-===##
+##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
 #
 #                     The LLVM Compiler Infrastructure
 #
 # This file is distributed under the University of Illinois Open Source
 # License. See LICENSE.TXT for details.
 #
-##===---------------------------------------------------------------------===##
+##===----------------------------------------------------------------------===##
 
 LEVEL = ../../..
 LIBRARYNAME = LLVMMipsCodeGen
diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h
index d9cdd4060a..05b4c5a070 100644
--- a/lib/Target/Mips/Mips.h
+++ b/lib/Target/Mips/Mips.h
@@ -1,16 +1,16 @@
-//===-- Mips.h - Top-level interface for Mips representation ---*- C++ -*-===//
+//===-- Mips.h - Top-level interface for Mips representation ----*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 // This file contains the entry points for global functions defined in
 // the LLVM Mips back-end.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #ifndef TARGET_MIPS_H
 #define TARGET_MIPS_H
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td
index e971339a02..b79016d788 100644
--- a/lib/Target/Mips/Mips.td
+++ b/lib/Target/Mips/Mips.td
@@ -1,23 +1,23 @@
-//===- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
+//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // This is the top level entry point for the Mips target.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Target-independent interfaces
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 include "llvm/Target/Target.td"
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 include "MipsRegisterInfo.td"
 include "MipsSchedule.td"
@@ -26,17 +26,16 @@ include "MipsCallingConv.td"
 
 def MipsInstrInfo : InstrInfo;
 
-//===---------------------------------------------------------------------===//
-// Mips Subtarget features                                                   //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// Mips Subtarget features                                                    //
+//===----------------------------------------------------------------------===//
 
 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
                                 "Support 64-bit FP registers.">;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
-                                "true",
-                                "Only supports single precision float">;
+                                "true", "Only supports single precision float">;
 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
                                 "Enable o32 ABI">;
 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
@@ -59,16 +58,16 @@ def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
                                 "Mips1 ISA Support">;
 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
                                 "Mips2 ISA Support">;
-def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion",
-                                "Mips32", "Mips32 ISA Support",
+def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
+                                "Mips32 ISA Support",
                                 [FeatureCondMov, FeatureBitCount]>;
 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
                                 "Mips32r2", "Mips32r2 ISA Support",
                                 [FeatureMips32, FeatureSEInReg]>;
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Mips processors supported.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, MipsGenericItineraries, Features>;
diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 6db64a504b..502f744e4d 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -1,16 +1,16 @@
-//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer -------------------===//
+//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-asm-printer"
 #include "Mips.h"
@@ -68,8 +68,7 @@ namespace {
     const char *getCurrentABIString() const;
     void emitFrameDirective();
 
-    void printInstruction(const MachineInstr *MI,
-                          raw_ostream &O); // autogen'd.
+    void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
     void EmitInstruction(const MachineInstr *MI) {
       SmallString<128> Str;
       raw_svector_ostream OS(Str);
@@ -78,8 +77,8 @@ namespace {
     }
     virtual void EmitFunctionBodyStart();
     virtual void EmitFunctionBodyEnd();
-    virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock
-                                                   *MBB) const;
+    virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
+                                                   MBB) const;
     static const char *getRegisterName(unsigned RegNo);
 
     virtual void EmitFunctionEntryLabel();
@@ -89,7 +88,7 @@ namespace {
 
 #include "MipsGenAsmWriter.inc"
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 //  Mips Asm Directives
 //
@@ -118,11 +117,11 @@ namespace {
 //    stack pointer subtration, the first register in the mask (RA) will be
 //    saved at address 48-8=40.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Mask directives
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 // Create a bitmask with all callee saved registers for CPU or Floating Point
 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
@@ -174,9 +173,9 @@ void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
     O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
 }
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Frame and Set directives
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 /// Frame Directive
 void MipsAsmPrinter::emitFrameDirective() {
@@ -238,8 +237,8 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() {
 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
 /// exactly one predecessor and the control transfer mechanism between
 /// the predecessor and this block is a fall-through.
-bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock
-                                                       *MBB) const {
+bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
+                                                       MBB) const {
   // The predecessor has to be immediately before this block.
   const MachineBasicBlock *Pred = *MBB->pred_begin();
 
@@ -392,8 +391,7 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
   // FIXME: Use SwitchSection.
 
   // Tell the assembler which ABI we are using
-  OutStreamer.EmitRawText("\t.section .mdebug." +
-                          Twine(getCurrentABIString()));
+  OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
 
   // TODO: handle O64 ABI
   if (Subtarget->isABI_EABI()) {
diff --git a/lib/Target/Mips/MipsCallingConv.td b/lib/Target/Mips/MipsCallingConv.td
index 63bc3fa5e5..8e4b216404 100644
--- a/lib/Target/Mips/MipsCallingConv.td
+++ b/lib/Target/Mips/MipsCallingConv.td
@@ -1,21 +1,21 @@
-//===- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
+//===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // This describes the calling conventions for Mips architecture.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 /// CCIfSubtarget - Match if the current subtarget has a feature F.
 class CCIfSubtarget<string F, CCAction A>:
   CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Mips O32 Calling Convention
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 // Only the return rules are defined here for O32. The rules for argument
 // passing are defined in MipsISelLowering.cpp.
@@ -30,9 +30,9 @@ def RetCC_MipsO32 : CallingConv<[
   CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
 ]>;
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Mips EABI Calling Convention
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 def CC_MipsEABI : CallingConv<[
   // Promote i8/i16 arguments to i32.
@@ -72,9 +72,9 @@ def RetCC_MipsEABI : CallingConv<[
   CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
 ]>;
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Mips Calling Convention Dispatch
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 def CC_Mips : CallingConv<[
   CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 08d4948200..b44a0af2d4 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -5,11 +5,11 @@
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 // Simple pass to fills delay slots with NOPs.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "delay-slot-filler"
 
diff --git a/lib/Target/Mips/MipsExpandPseudo.cpp b/lib/Target/Mips/MipsExpandPseudo.cpp
index cf6105db65..4423f51479 100644
--- a/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -1,16 +1,16 @@
-//===--  MipsExpandPseudo.cpp - Expand pseudo instructions ---------------===//
+//===--  MipsExpandPseudo.cpp - Expand pseudo instructions ----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
-// This pass expands pseudo instructions into target instructions after
-// register allocation but before post-RA scheduling.
+// This pass expands pseudo instructions into target instructions after register
+// allocation but before post-RA scheduling.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-expand-pseudo"
 
@@ -86,8 +86,7 @@ bool MipsExpandPseudo::runOnMachineBasicBlock(MachineBasicBlock& MBB) {
 void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
                                             MachineBasicBlock::iterator I) {  
   unsigned DstReg = I->getOperand(0).getReg();
-  unsigned LoReg = I->getOperand(1).getReg();
-  unsigned HiReg = I->getOperand(2).getReg();
+  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
   const TargetInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
   DebugLoc dl = I->getDebugLoc();
   const unsigned* SubReg =
diff --git a/lib/Target/Mips/MipsFrameLowering.cpp b/lib/Target/Mips/MipsFrameLowering.cpp
index ded6e850f7..21e3314a66 100644
--- a/lib/Target/Mips/MipsFrameLowering.cpp
+++ b/lib/Target/Mips/MipsFrameLowering.cpp
@@ -1,15 +1,15 @@
-//=======- MipsFrameLowering.cpp - Mips Frame Information -----*- C++ -*-====//
+//=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 // This file contains the Mips implementation of TargetFrameLowering class.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #include "MipsFrameLowering.h"
 #include "MipsInstrInfo.h"
@@ -27,7 +27,7 @@
 using namespace llvm;
 
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 // Stack Frame Processing methods
 // +----------------------------+
@@ -77,11 +77,11 @@ using namespace llvm;
 // possible to detect those references and the offsets are adjusted to
 // their real location.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 // hasFP - Return true if the specified function should have a dedicated frame
-// pointer register.  This is true if the function has variable sized allocas
-// or if frame pointer elimination is disabled.
+// pointer register.  This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
@@ -203,6 +203,7 @@ void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
     MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
 }
 
+
 // expand pair of register and immediate if the immediate doesn't fit in the
 // 16-bit offset field.
 // e.g.
@@ -228,7 +229,7 @@ static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
   DebugLoc DL = I->getDebugLoc();
   int ImmLo = OrigImm & 0xffff;
-  int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + 
+  int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
               ((OrigImm & 0x8000) != 0);
 
   // FIXME: change this when mips goes MC".
diff --git a/lib/Target/Mips/MipsFrameLowering.h b/lib/Target/Mips/MipsFrameLowering.h
index 590071c07a..34647df4f3 100644
--- a/lib/Target/Mips/MipsFrameLowering.h
+++ b/lib/Target/Mips/MipsFrameLowering.h
@@ -1,15 +1,15 @@
-//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*--===//
+//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*---===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 //
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #ifndef MIPS_FRAMEINFO_H
 #define MIPS_FRAMEINFO_H
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index ab1737f398..0382964fe9 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -1,15 +1,15 @@
-//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips -------===//
+//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 // This file defines an instruction selector for the MIPS target.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-isel"
 #include "Mips.h"
@@ -34,14 +34,14 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Instruction Selector Implementation
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
 // instructions for SelectionDAG operations.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 namespace {
 
 class MipsDAGToDAGISel : public SelectionDAGISel {
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index fef720c80f..cde9fb3350 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -1,16 +1,16 @@
-//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation ----------===//
+//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that Mips uses to lower LLVM code into a
 // selection DAG.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-lower"
 #include "MipsISelLowering.h"
@@ -221,8 +221,8 @@ static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
   // Transform this to a MADD only if ADDENode and ADDCNode are the only users
   // of the values of MultNode, in which case MultNode will be removed in later
   // phases.
-  // If there exist users other than ADDENode or ADDCNode, this function
-  // returns here, which will result in MultNode being mapped to a single MULT
+  // If there exist users other than ADDENode or ADDCNode, this function returns
+  // here, which will result in MultNode being mapped to a single MULT
   // instruction node rather than a pair of MULT and MADD instructions being
   // produced.
   if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
@@ -295,8 +295,8 @@ static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
   // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
   // of the values of MultNode, in which case MultNode will be removed in later
   // phases.
-  // If there exist users other than SUBENode or SUBCNode, this function
-  // returns here, which will result in MultNode being mapped to a single MULT
+  // If there exist users other than SUBENode or SUBCNode, this function returns
+  // here, which will result in MultNode being mapped to a single MULT
   // instruction node rather than a pair of MULT and MSUB instructions being
   // produced.
   if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
@@ -520,9 +520,9 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
   return SDValue();
 }
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //  Lower helper functions
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 // AddLiveIn - This helper function adds the specified physical register to the
 // MachineFunction as a live in value.  It also creates a corresponding
@@ -653,9 +653,9 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   return BB;
 }
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //  Misc Lower Operation implementation
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 SDValue MipsTargetLowering::
 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
@@ -880,11 +880,9 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
 
   if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
     SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
-                                             N->getOffset(),
-                                             MipsII::MO_ABS_HI);
+                                             N->getOffset(), MipsII::MO_ABS_HI);
     SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
-                                             N->getOffset(),
-                                             MipsII::MO_ABS_LO);
+                                             N->getOffset(), MipsII::MO_ABS_LO);
     SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
     SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
     ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
@@ -895,8 +893,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
                                CP, MachinePointerInfo::getConstantPool(),
                                false, false, 0);
     SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
-                                             N->getOffset(),
-                                             MipsII::MO_ABS_LO);
+                                             N->getOffset(), MipsII::MO_ABS_LO);
     SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
     ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
   }
@@ -920,13 +917,13 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
                       false, false, 0);
 }
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #include "MipsGenCallingConv.inc"
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // TODO: Implement a generic logic using tblgen that can support this.
 // Mips O32 ABI rules:
 // ---
@@ -937,7 +934,7 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
 //       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
 //       not used, it must be shadowed. If only A3 is avaiable, shadow it and
 //       go to stack.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,