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authorBill Wendling <isanbard@gmail.com>2010-11-08 23:50:20 +0000
committerBill Wendling <isanbard@gmail.com>2010-11-08 23:50:20 +0000
commit3734ef3fb478cbae7baedfe009519a51db3b095e (patch)
tree2fc3671f3b69658a45fb25832346fd217a084843 /lib
parent87f4f9a946549ad93046990a364ac5190333a7eb (diff)
reglist has two operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 7c7257900f..0a988138a9 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -278,6 +278,7 @@ def brtarget : Operand<OtherVT>;
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
+ int NumOperands = 2;
string EncoderMethod = "getRegisterListOpValue";
let PrintMethod = "printRegisterList";
}