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authorRafael Espindola <rafael.espindola@gmail.com>2006-09-11 19:23:32 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-09-11 19:23:32 +0000
commit1b3956b516e28d634e48a12074b94acca5bcc679 (patch)
tree4c358143aa81f9141532a466f4210cd33445be46 /lib
parentb082f8648b9d9c90c18dc3552b83717fb8498e81 (diff)
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30261 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp9
1 files changed, 3 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 353e3fccf4..c356f09a69 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -482,19 +482,16 @@ static bool isInt12Immediate(SDOperand Op, short &Imm) {
bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
SDOperand &Arg) {
switch(N.getOpcode()) {
- case ISD::CopyFromReg:
- Arg = N;
- return true;
case ISD::Constant: {
//TODO:check that we have a valid constant
int32_t t = cast<ConstantSDNode>(N)->getValue();
Arg = CurDAG->getTargetConstant(t, MVT::i32);
return true;
}
- default:
- std::cerr << "OpCode = " << N.getOpcode() << "\n";
- assert(0);
}
+
+ Arg = N;
+ return true;
}
//register plus/minus 12 bit offset