First patch in the direction of splitting MachineCodeEmitter in two subclasses:

JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8

24 files changed, 551 insertions, 237 deletions

diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h
index b275d2a8d8..c582d684bf 100644
--- a/lib/Target/ARM/ARM.h
+++ b/lib/Target/ARM/ARM.h
@@ -23,6 +23,7 @@ namespace llvm {
 class ARMTargetMachine;
 class FunctionPass;
 class MachineCodeEmitter;
+class JITCodeEmitter;
 class raw_ostream;
 
 // Enums corresponding to ARM condition codes
@@ -96,6 +97,17 @@ FunctionPass *createARMCodePrinterPass(raw_ostream &O,
                                        bool Verbose);
 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
+
+FunctionPass *createARMCodeEmitterPass(
+    ARMTargetMachine &TM, MachineCodeEmitter &MCE);
+/*
+template< class machineCodeEmitter>
+FunctionPass *createARMCodeEmitterPass(
+    ARMTargetMachine &TM, machineCodeEmitter &MCE);
+*/
+FunctionPass *createARMJITCodeEmitterPass(
+    ARMTargetMachine &TM, JITCodeEmitter &JCE);
+
 FunctionPass *createARMLoadStoreOptimizationPass();
 FunctionPass *createARMConstantIslandPass();
 
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index c27fc5f1ea..70b5d788b4 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -25,6 +25,7 @@
 #include "llvm/Function.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
@@ -41,23 +42,37 @@ using namespace llvm;
 STATISTIC(NumEmitted, "Number of machine instructions emitted");
 
 namespace {
-  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
+
+  class ARMCodeEmitter {
+  public:
+
+    /// getBinaryCodeForInstr - This function, generated by the
+    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
+    /// machine instructions.
+
+    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
+  };
+
+  template< class machineCodeEmitter>	
+  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, 
+    	public ARMCodeEmitter
+  {
     ARMJITInfo                *JTI;
     const ARMInstrInfo        *II;
     const TargetData          *TD;
     TargetMachine             &TM;
-    MachineCodeEmitter        &MCE;
+    machineCodeEmitter        &MCE;
     const std::vector<MachineConstantPoolEntry> *MCPEs;
     const std::vector<MachineJumpTableEntry> *MJTEs;
     bool IsPIC;
 
   public:
     static char ID;
-    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
+    explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce)
       : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
       MCE(mce), MCPEs(0), MJTEs(0),
       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
-    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
+    Emitter(TargetMachine &tm, machineCodeEmitter &mce,
             const ARMInstrInfo &ii, const TargetData &td)
       : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
       MCE(mce), MCPEs(0), MJTEs(0),
@@ -134,12 +149,6 @@ namespace {
 
     void emitMiscInstruction(const MachineInstr &MI);
 
-    /// getBinaryCodeForInstr - This function, generated by the
-    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
-    /// machine instructions.
-    ///
-    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
-
     /// getMachineOpValue - Return binary encoding of operand. If the machine
     /// operand requires relocation, record the relocation and return zero.
     unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
@@ -161,17 +170,30 @@ namespace {
     void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
                                intptr_t JTBase = 0);
   };
-  char ARMCodeEmitter::ID = 0;
+  template <class machineCodeEmitter>
+  char Emitter<machineCodeEmitter>::ID = 0;
 }
 
 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
 /// to the specified MCE object.
-FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
-                                             MachineCodeEmitter &MCE) {
-  return new ARMCodeEmitter(TM, MCE);
+
+namespace llvm {
+	
+FunctionPass *createARMCodeEmitterPass(
+    ARMTargetMachine &TM, MachineCodeEmitter &MCE)
+{
+  return new Emitter<MachineCodeEmitter>(TM, MCE);
+}
+FunctionPass *createARMJITCodeEmitterPass(
+    ARMTargetMachine &TM, JITCodeEmitter &JCE)
+{
+  return new Emitter<JITCodeEmitter>(TM, JCE);
 }
 
-bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+} // end namespace llvm
+
+template< class machineCodeEmitter>
+bool Emitter< machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
   assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
           MF.getTarget().getRelocationModel() != Reloc::Static) &&
          "JIT relocation model must be set to static or default!");
@@ -200,7 +222,8 @@ bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
 
 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
 ///
-unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getShiftOp(unsigned Imm) const {
   switch (ARM_AM::getAM2ShiftOpc(Imm)) {
   default: assert(0 && "Unknown shift opc!");
   case ARM_AM::asr: return 2;
@@ -214,7 +237,8 @@ unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
 
 /// getMachineOpValue - Return binary encoding of operand. If the machine
 /// operand requires relocation, record the relocation and return zero.
-unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getMachineOpValue(const MachineInstr &MI,
                                            const MachineOperand &MO) {
   if (MO.isReg())
     return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
@@ -243,7 +267,8 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
 
 /// emitGlobalAddress - Emit the specified address to the code stream.
 ///
-void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
                                        bool NeedStub, intptr_t ACPV) {
   MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
                                              Reloc, GV, ACPV, NeedStub));
@@ -252,7 +277,8 @@ void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
 /// be emitted to the current location in the function, and allow it to be PC
 /// relative.
-void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
                                                  Reloc, ES));
 }
@@ -260,7 +286,8 @@ void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
 /// emitConstPoolAddress - Arrange for the address of an constant pool
 /// to be emitted to the current location in the function, and allow it to be PC
 /// relative.
-void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
   // Tell JIT emitter we'll resolve the address.
   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
                                                     Reloc, CPI, 0, true));
@@ -269,19 +296,22 @@ void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
 /// emitJumpTableAddress - Arrange for the address of a jump table to
 /// be emitted to the current location in the function, and allow it to be PC
 /// relative.
-void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
                                                     Reloc, JTIndex, 0, true));
 }
 
 /// emitMachineBasicBlock - Emit the specified address basic block.
-void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
                                            unsigned Reloc, intptr_t JTBase) {
   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
                                              Reloc, BB, JTBase));
 }
 
-void ARMCodeEmitter::emitWordLE(unsigned Binary) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitWordLE(unsigned Binary) {
 #ifndef NDEBUG
   DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
        << Binary << std::dec << "\n";
@@ -289,7 +319,8 @@ void ARMCodeEmitter::emitWordLE(unsigned Binary) {
   MCE.emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitDWordLE(uint64_t Binary) {
 #ifndef NDEBUG
   DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
        << (unsigned)Binary << std::dec << "\n";
@@ -299,7 +330,8 @@ void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
   MCE.emitDWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitInstruction(const MachineInstr &MI) {
   DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
 
   NumEmitted++;  // Keep track of the # of mi's emitted
@@ -365,7 +397,8 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
   }
 }
 
-void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
   unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
   unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
   const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
@@ -432,7 +465,8 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
   }
 }
 
-void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
   const MachineOperand &MO0 = MI.getOperand(0);
   const MachineOperand &MO1 = MI.getOperand(1);
   assert(MO1.isImm() && "Not a valid so_imm value!");
@@ -473,7 +507,8 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
   // It's basically add r, pc, (LJTI - $+8)
   
   const TargetInstrDesc &TID = MI.getDesc();
@@ -501,7 +536,8 @@ void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
   unsigned Opcode = MI.getDesc().Opcode;
 
   // Part of binary is determined by TableGn.
@@ -540,13 +576,15 @@ void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::addPCLabel(unsigned LabelID) {
   DOUT << "  ** LPC" << LabelID << " @ "
        << (void*)MCE.getCurrentPCValue() << '\n';
   JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
 }
 
-void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
   unsigned Opcode = MI.getDesc().Opcode;
   switch (Opcode) {
   default:
@@ -615,8 +653,8 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
   }
 }
 
-
-unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getMachineSoRegOpValue(const MachineInstr &MI,
                                                 const TargetInstrDesc &TID,
                                                 const MachineOperand &MO,
                                                 unsigned OpIdx) {
@@ -674,7 +712,8 @@ unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
   return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
 }
 
-unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
   // Encode rotate_imm.
   unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
     << ARMII::SoRotImmShift;
@@ -684,7 +723,8 @@ unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
   return Binary;
 }
 
-unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
                                          const TargetInstrDesc &TID) const {
   for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
     const MachineOperand &MO = MI.getOperand(i-1);
@@ -694,7 +734,8 @@ unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
   return 0;
 }
 
-void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitDataProcessingInstruction(const MachineInstr &MI,
                                                    unsigned ImplicitRd,
                                                    unsigned ImplicitRn) {
   const TargetInstrDesc &TID = MI.getDesc();
@@ -757,7 +798,8 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitLoadStoreInstruction(const MachineInstr &MI,
                                               unsigned ImplicitRd,
                                               unsigned ImplicitRn) {
   const TargetInstrDesc &TID = MI.getDesc();
@@ -831,7 +873,8 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
                                                   unsigned ImplicitRn) {
   const TargetInstrDesc &TID = MI.getDesc();
   unsigned Form = TID.TSFlags & ARMII::FormMask;
@@ -914,7 +957,8 @@ static unsigned getAddrModeUPBits(unsigned Mode) {
   return Binary;
 }
 
-void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
@@ -946,7 +990,8 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
   const TargetInstrDesc &TID = MI.getDesc();
 
   // Part of binary is determined by TableGn.
@@ -983,7 +1028,8 @@ void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
   const TargetInstrDesc &TID = MI.getDesc();
 
   // Part of binary is determined by TableGn.
@@ -1020,7 +1066,8 @@ void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
   const TargetInstrDesc &TID = MI.getDesc();
 
   // Part of binary is determined by TableGn.
@@ -1058,7 +1105,8 @@ void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
   const TargetInstrDesc &TID = MI.getDesc();
 
   if (TID.Opcode == ARM::TPsoft)
@@ -1076,7 +1124,8 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
   // Remember the base address of the inline jump table.
   uintptr_t JTBase = MCE.getCurrentPCValue();
   JTI->addJumpTableBaseAddr(JTIndex, JTBase);
@@ -1095,7 +1144,8 @@ void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
   }
 }
 
-void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
   const TargetInstrDesc &TID = MI.getDesc();
 
   // Handle jump tables.
@@ -1175,7 +1225,8 @@ static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
   return Binary;
 }
 
-void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
   const TargetInstrDesc &TID = MI.getDesc();
 
   // Part of binary is determined by TableGn.
@@ -1214,7 +1265,8 @@ void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPConversionInstruction(const MachineInstr &MI) {
   const TargetInstrDesc &TID = MI.getDesc();
   unsigned Form = TID.TSFlags & ARMII::FormMask;
 
@@ -1270,7 +1322,8 @@ void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
@@ -1304,8 +1357,8 @@ void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void
-ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
@@ -1339,7 +1392,8 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
   emitWordLE(Binary);
 }
 
-void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
@@ -1350,3 +1404,4 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
 }
 
 #include "ARMGenCodeEmitter.inc"
+
diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp
index eda0c93366..e551c41936 100644
--- a/lib/Target/ARM/ARMJITInfo.cpp
+++ b/lib/Target/ARM/ARMJITInfo.cpp
@@ -18,7 +18,7 @@
 #include "ARMRelocations.h"
 #include "ARMSubtarget.h"
 #include "llvm/Function.h"
-#include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
 #include "llvm/Config/alloca.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Streams.h"
@@ -141,16 +141,16 @@ ARMJITInfo::getLazyResolverFunction(JITCompilerFn F) {
 }
 
 void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr,
-                                             MachineCodeEmitter &MCE) {
-  MCE.startGVStub(GV, 4, 4);
-  MCE.emitWordLE((intptr_t)Ptr);
-  void *PtrAddr = MCE.finishGVStub(GV);
+                                             JITCodeEmitter &JCE) {
+  JCE.startGVStub(GV, 4, 4);
+  JCE.emitWordLE((intptr_t)Ptr);
+  void *PtrAddr = JCE.finishGVStub(GV);
   addIndirectSymAddr(Ptr, (intptr_t)PtrAddr);
   return PtrAddr;
 }
 
 void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
-                                   MachineCodeEmitter &MCE) {
+                                   JITCodeEmitter &JCE) {
   // If this is just a call to an external function, emit a branch instead of a
   // call.  The code is the same except for one bit of the last instruction.
   if (Fn != (void*)(intptr_t)ARMCompilationCallback) {
@@ -160,7 +160,7 @@ void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
       intptr_t LazyPtr = getIndirectSymAddr(Fn);
       if (!LazyPtr) {
         // In PIC mode, the function stub is loading a lazy-ptr.
-        LazyPtr= (intptr_t)emitGlobalValueIndirectSym((GlobalValue*)F, Fn, MCE);
+        LazyPtr= (intptr_t)emitGlobalValueIndirectSym((GlobalValue*)F, Fn, JCE);
         if (F)
           DOUT << "JIT: Indirect symbol emitted at [" << LazyPtr << "] for GV '"
                << F->getName() << "'\n";
@@ -168,19 +168,19 @@ void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
           DOUT << "JIT: Stub emitted at [" << LazyPtr
                << "] for external function at '" << Fn << "'\n";
       }
-      MCE.startGVStub(F, 16, 4);
-      intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
-      MCE.emitWordLE(0xe59fc004);            // ldr pc, [pc, #+4]
-      MCE.emitWordLE(0xe08fc00c);            // L_func$scv: add ip, pc, ip
-      MCE.emitWordLE(0xe59cf000);            // ldr pc, [ip]
-      MCE.emitWordLE(LazyPtr - (Addr+4+8));  // func - (L_func$scv+8)
+      JCE.startGVStub(F, 16, 4);
+      intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
+      JCE.emitWordLE(0xe59fc004);            // ldr pc, [pc, #+4]
+      JCE.emitWordLE(0xe08fc00c);            // L_func$scv: add ip, pc, ip
+      JCE.emitWordLE(0xe59cf000);            // ldr pc, [ip]
+      JCE.emitWordLE(LazyPtr - (Addr+4+8));  // func - (L_func$scv+8)
       sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
     } else {
       // The stub is 8-byte size and 4-aligned.
-      MCE.startGVStub(F, 8, 4);
-      intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
-      MCE.emitWordLE(0xe51ff004);    // ldr pc, [pc, #-4]
-      MCE.emitWordLE((intptr_t)Fn);  // addr of function
+      JCE.startGVStub(F, 8, 4);
+      intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
+      JCE.emitWordLE(0xe51ff004);    // ldr pc, [pc, #-4]
+      JCE.emitWordLE((intptr_t)Fn);  // addr of function
       sys::Memory::InvalidateInstructionCache((void*)Addr, 8);
     }
   } else {
@@ -191,22 +191,22 @@ void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
     //
     // Branch and link to the compilation callback.
     // The stub is 16-byte size and 4-byte aligned.
-    MCE.startGVStub(F, 16, 4);
-    intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
+    JCE.startGVStub(F, 16, 4);
+    intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
     // Save LR so the callback can determine which stub called it.
     // The compilation callback is responsible for popping this prior
     // to returning.
-    MCE.emitWordLE(0xe92d4000); // push {lr}
+    JCE.emitWordLE(0xe92d4000); // push {lr}
     // Set the return address to go back to the start of this stub.
-    MCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12
+    JCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12
     // Invoke the compilation callback.
-    MCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
+    JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
     // The address of the compilation callback.
-    MCE.emitWordLE((intptr_t)ARMCompilationCallback);
+    JCE.emitWordLE((intptr_t)ARMCompilationCallback);
     sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
   }
 
-  return MCE.finishGVStub(F);
+  return JCE.finishGVStub(F);
 }
 
 intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const {
diff --git a/lib/Target/ARM/ARMJITInfo.h b/lib/Target/ARM/ARMJITInfo.h
index 8bcaa4c066..7dfeed8b7b 100644
--- a/lib/Target/ARM/ARMJITInfo.h
+++ b/lib/Target/ARM/ARMJITInfo.h
@@ -55,17 +55,17 @@ namespace llvm {
     ///
     virtual void replaceMachineCodeForFunction(void *Old, void *New);
 
-    /// emitGlobalValueIndirectSym - Use the specified MachineCodeEmitter object
+    /// emitGlobalValueIndirectSym - Use the specified JITCodeEmitter object
     /// to emit an indirect symbol which contains the address of the specified
     /// ptr.
     virtual void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
-                                            MachineCodeEmitter &MCE);
+                                            JITCodeEmitter &JCE);
 
-    /// emitFunctionStub - Use the specified MachineCodeEmitter object to emit a
+    /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
     /// small native function that simply calls the function at the specified
     /// address.
     virtual void *emitFunctionStub(const Function* F, void *Fn,
-                                   MachineCodeEmitter &MCE);
+                                   JITCodeEmitter &JCE);
 
     /// getLazyResolverFunction - Expose the lazy resolver to the JIT.
     virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
@@ -86,7 +86,7 @@ namespace llvm {
 
     /// allocateSeparateGVMemory - If true, globals should be placed in
     /// separately allocated heap memory rather than in the same
-    /// code memory allocated by MachineCodeEmitter.
+    /// code memory allocated by JITCodeEmitter.
     virtual bool allocateSeparateGVMemory() const {
 #ifdef __APPLE__
       return true;
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index a5ce86e9df..1dc7d19aa1 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -190,6 +190,25 @@ bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
   return false;
 }
 
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel,
+                                      bool DumpAsm,
+                                      JITCodeEmitter &JCE) {
+  // FIXME: Move this to TargetJITInfo!
+  if (DefRelocModel == Reloc::Default)
+    setRelocationModel(Reloc::Static);
+
+  // Machine code emitter pass for ARM.
+  PM.add(createARMJITCodeEmitterPass(*this, JCE));
+  if (DumpAsm) {
+    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+    if (AsmPrinterCtor)
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+  }
+
+  return false;
+}
+
 bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
                                             CodeGenOpt::Level OptLevel,
                                             bool DumpAsm,
@@ -204,3 +223,20 @@ bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 
   return false;
 }
+
+bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                            CodeGenOpt::Level OptLevel,
+                                            bool DumpAsm,
+                                            JITCodeEmitter &JCE) {
+  // Machine code emitter pass for ARM.
+  PM.add(createARMJITCodeEmitterPass(*this, JCE));
+  if (DumpAsm) {
+    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
+    if (AsmPrinterCtor)
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+  }
+
+  return false;
+}
+
+
diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h
index 3f65f71bbe..916a8aa9e9 100644
--- a/lib/Target/ARM/ARMTargetMachine.h
+++ b/lib/Target/ARM/ARMTargetMachine.h
@@ -77,10 +77,16 @@ public:
                                   bool Verbose, raw_ostream &Out);
   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
+  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+                              bool DumpAsm, JITCodeEmitter &MCE);
   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
                                     CodeGenOpt::Level OptLevel,
                                     bool DumpAsm,
                                     MachineCodeEmitter &MCE);
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+                                    CodeGenOpt::Level OptLevel,
+                                    bool DumpAsm,
+                                    JITCodeEmitter &MCE);
 };
 
 /// ThumbTargetMachine - Thumb target machine.
diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h
index 853109ae34..2815176149 100644
--- a/lib/Target/Alpha/Alpha.h
+++ b/lib/Target/Alpha/Alpha.h
@@ -32,6 +32,8 @@ namespace llvm {