diff options
author | Duncan Sands <baldrick@free.fr> | 2012-02-05 14:20:11 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2012-02-05 14:20:11 +0000 |
commit | 5b8a1db7ea6510a2589f710d50754599da742de9 (patch) | |
tree | b0fc32da198a889ddd064c49ae7e8597bfe1eab4 /lib/Target | |
parent | 853066a32af39c4674d47713e64b8ed9859976f9 (diff) |
Persuade GCC that there is nothing worth warning about here (there isn't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 1 | ||||
-rw-r--r-- | lib/Target/X86/Disassembler/X86DisassemblerDecoder.c | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 |
3 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 63c516109e..79c447af2c 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -2279,6 +2279,7 @@ bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len) assert (RV == true && "Should be able to handle this load."); RV = ARMEmitStore(VT, ResultReg, Dest); assert (RV == true && "Should be able to handle this store."); + (void)RV; unsigned Size = VT.getSizeInBits()/8; Len -= Size; diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c index bb24d33131..958f653eb7 100644 --- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c +++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c @@ -103,7 +103,7 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM) { - const struct ModRMDecision* dec; + const struct ModRMDecision* dec = 0; switch (type) { case ONEBYTE: diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 7c3faca1db..81396cca2e 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8288,7 +8288,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { if (isFP) { unsigned SSECC = 8; EVT EltVT = Op0.getValueType().getVectorElementType(); - assert(EltVT == MVT::f32 || EltVT == MVT::f64); + assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; bool Swap = false; |