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authorChris Lattner <sabre@nondot.org>2004-04-06 03:36:57 +0000
committerChris Lattner <sabre@nondot.org>2004-04-06 03:36:57 +0000
commit0652167bea9d00ac855ddf93883365f8f651f2f8 (patch)
tree0b15d140e5531cf7406ea6eaf06eb0eadc5e7915 /lib/Target/X86/InstSelectSimple.cpp
parent92900a65a362947010d22ff1998f722097044961 (diff)
Bugfixes: inc/dec don't set the carry flag!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12687 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/InstSelectSimple.cpp')
-rw-r--r--lib/Target/X86/InstSelectSimple.cpp20
1 files changed, 8 insertions, 12 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 264a1373de..e735f94e7f 100644
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -1742,24 +1742,20 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
}
// add X, -1 -> dec X
- if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
- static unsigned const DECTab[] = {
- X86::DEC8r, X86::DEC16r, X86::DEC32r, 0, X86::DEC32r
- };
+ if (OperatorClass == 0 && Op1C->isAllOnesValue() && Class != cLong) {
+ // Note that we can't use dec for 64-bit decrements, because it does not
+ // set the carry flag!
+ static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
- if (Class == cLong) // Dh = sbb Sh, 0
- BuildMI(*MBB, IP, X86::SBB32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
return;
}
// add X, 1 -> inc X
- if (OperatorClass == 0 && Op1C->equalsInt(1)) {
- static unsigned const INCTab[] = {
- X86::INC8r, X86::INC16r, X86::INC32r, 0, X86::INC32r
- };
+ if (OperatorClass == 0 && Op1C->equalsInt(1) && Class != cLong) {
+ // Note that we can't use inc for 64-bit increments, because it does not
+ // set the carry flag!
+ static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
- if (Class == cLong) // Dh = adc Sh, 0
- BuildMI(*MBB, IP, X86::ADC32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
return;
}