diff options
| author | David Blaikie <dblaikie@gmail.com> | 2011-12-20 02:50:00 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2011-12-20 02:50:00 +0000 |
| commit | 2d24e2a396a1d211baaeedf32148a3b657240170 (patch) | |
| tree | 756132115ff4a5abb85dfbd38cef66e0d36efcb1 /lib/Target/Mips/MipsTargetMachine.cpp | |
| parent | 1885687462c5fc6094f56d8d5f3ce0a71ae157e4 (diff) | |
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsTargetMachine.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsTargetMachine.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 02887fa9a4..6088ceedcc 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -52,6 +52,8 @@ MipsTargetMachine(const Target &T, StringRef TT, TLInfo(*this), TSInfo(*this), JITInfo() { } +void MipsebTargetMachine::anchor() { } + MipsebTargetMachine:: MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -59,6 +61,8 @@ MipsebTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} +void MipselTargetMachine::anchor() { } + MipselTargetMachine:: MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -66,6 +70,8 @@ MipselTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} +void Mips64ebTargetMachine::anchor() { } + Mips64ebTargetMachine:: Mips64ebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -73,6 +79,8 @@ Mips64ebTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} +void Mips64elTargetMachine::anchor() { } + Mips64elTargetMachine:: Mips64elTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, |