CellSPU:

- Add preliminary support for v2i32; load/store generates the right code but
  there's a lot work to be done to make this vector type operational.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61829 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 8 deletions

diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 6a0fde398b..b9956402d9 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -71,6 +71,8 @@ let canFoldAsLoad = 1 in {
     def v4f32: LoadDFormVec<v4f32>;
     def v2f64: LoadDFormVec<v2f64>;
 
+    def v2i32: LoadDFormVec<v2i32>;
+
     def r128:  LoadDForm<GPRC>;
     def r64:   LoadDForm<R64C>;
     def r32:   LoadDForm<R32C>;
@@ -103,6 +105,8 @@ let canFoldAsLoad = 1 in {
     def v4f32: LoadAFormVec<v4f32>;
     def v2f64: LoadAFormVec<v2f64>;
 
+    def v2i32: LoadAFormVec<v2i32>;
+
     def r128:  LoadAForm<GPRC>;
     def r64:   LoadAForm<R64C>;
     def r32:   LoadAForm<R32C>;
@@ -135,6 +139,8 @@ let canFoldAsLoad = 1 in {
     def v4f32: LoadXFormVec<v4f32>;
     def v2f64: LoadXFormVec<v2f64>;
 
+    def v2i32: LoadXFormVec<v2i32>;
+
     def r128:  LoadXForm<GPRC>;
     def r64:   LoadXForm<R64C>;
     def r32:   LoadXForm<R32C>;
@@ -183,6 +189,8 @@ multiclass StoreDForms
   def v4f32: StoreDFormVec<v4f32>;
   def v2f64: StoreDFormVec<v2f64>;
 
+  def v2i32: StoreDFormVec<v2i32>;
+
   def r128:  StoreDForm<GPRC>;
   def r64:   StoreDForm<R64C>;
   def r32:   StoreDForm<R32C>;
@@ -213,6 +221,8 @@ multiclass StoreAForms
   def v4f32: StoreAFormVec<v4f32>;
   def v2f64: StoreAFormVec<v2f64>;
 
+  def v2i32: StoreAFormVec<v2i32>;
+
   def r128:  StoreAForm<GPRC>;
   def r64:   StoreAForm<R64C>;
   def r32:   StoreAForm<R32C>;
@@ -245,6 +255,8 @@ multiclass StoreXForms
   def v4f32: StoreXFormVec<v4f32>;
   def v2f64: StoreXFormVec<v2f64>;
 
+  def v2i32: StoreXFormVec<v2i32>;
+
   def r128:  StoreXForm<GPRC>;
   def r64:   StoreXForm<R64C>;
   def r32:   StoreXForm<R32C>;
@@ -1044,11 +1056,11 @@ class GBBInst<dag OOL, dag IOL, list<dag> pattern>:
 
 class GBBRegInst<RegisterClass rclass, ValueType vectype>:
   GBBInst<(outs rclass:$rT), (ins VECREG:$rA),
-          [(set rclass:$rT, (SPUgatherbits (vectype VECREG:$rA)))]>;
+          [/* no pattern */]>;
 
 class GBBVecInst<ValueType vectype>:
   GBBInst<(outs VECREG:$rT), (ins VECREG:$rA),
-          [(set (vectype VECREG:$rT), (SPUgatherbits (vectype VECREG:$rA)))]>;
+          [/* no pattern */]>;
 
 multiclass GatherBitsFromBytes {
   def v16i8_r32: GBBRegInst<R32C, v16i8>;
@@ -1070,12 +1082,11 @@ class GBHInst<dag OOL, dag IOL, list<dag> pattern>:
 
 class GBHRegInst<RegisterClass rclass, ValueType vectype>:
     GBHInst<(outs rclass:$rT), (ins VECREG:$rA),
-            [(set rclass:$rT, (SPUgatherbits (vectype VECREG:$rA)))]>;
+            [/* no pattern */]>;
 
 class GBHVecInst<ValueType vectype>:
     GBHInst<(outs VECREG:$rT), (ins VECREG:$rA),
-            [(set (vectype VECREG:$rT),
-                  (SPUgatherbits (vectype VECREG:$rA)))]>;
+            [/* no pattern */]>;
 
 multiclass GatherBitsHalfword {
   def v8i16_r32: GBHRegInst<R32C, v8i16>;
@@ -1097,12 +1108,11 @@ class GBInst<dag OOL, dag IOL, list<dag> pattern>:
 
 class GBRegInst<RegisterClass rclass, ValueType vectype>:
     GBInst<(outs rclass:$rT), (ins VECREG:$rA),
-           [(set rclass:$rT, (SPUgatherbits (vectype VECREG:$rA)))]>;
+           [/* no pattern */]>;
 
 class GBVecInst<ValueType vectype>:
     GBInst<(outs VECREG:$rT), (ins VECREG:$rA),
-           [(set (vectype VECREG:$rT),
-                 (SPUgatherbits (vectype VECREG:$rA)))]>;
+           [/* no pattern */]>;
 
 multiclass GatherBitsWord {
   def v4i32_r32: GBRegInst<R32C, v4i32>;