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| author | Jim Grosbach <grosbach@apple.com> | 2011-09-16 20:50:13 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-09-16 20:50:13 +0000 |
| commit | 8213c96655e955a0b63b05580bc2f6a55be26083 (patch) | |
| tree | 161ff9f764823e36c02c738b37dca73a9f3a1399 /lib/Target/ARM | |
| parent | ffee5728affd21b563c9f6b11a5029aa7fcb7bc2 (diff) | |
Thumb2 assembly parsing and encoding for STMIA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 15 |
2 files changed, 17 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 1d86a2a80b..4d15b0201d 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3861,3 +3861,6 @@ def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn", (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>; +// STM w/o the .w suffix. +def : t2InstAlias<"stm${p} $Rn, $regs", + (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 51651e4b26..149c46f28c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3679,7 +3679,7 @@ validateInstruction(MCInst &Inst, } case ARM::tSTMIA_UPD: { bool listContainsBase; - if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase)) + if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) return Error(Operands[4]->getStartLoc(), "registers must be in range r0-r7"); break; @@ -3778,6 +3778,19 @@ processInstruction(MCInst &Inst, } break; } + case ARM::tSTMIA_UPD: { + // If the register list contains any high registers, we need to use + // the 32-bit encoding instead if we're in Thumb2. Otherwise, this + // should have generated an error in validateInstruction(). + unsigned Rn = Inst.getOperand(0).getReg(); + bool listContainsBase; + if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { + // 16-bit encoding isn't sufficient. Switch to the 32-bit version. + assert (isThumbTwo()); + Inst.setOpcode(ARM::t2STMIA_UPD); + } + break; + } case ARM::t2MOVi: { // If we can use the 16-bit encoding and the user didn't explicitly // request the 32-bit variant, transform it here. |