diff options
| author | Bill Wendling <isanbard@gmail.com> | 2011-10-22 00:29:28 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2011-10-22 00:29:28 +0000 |
| commit | b8dcb314f7f9c5c0f068a322c689a64881d78b70 (patch) | |
| tree | e26e2d02abcac88f2738104a9a7183d4375a02bd /lib/Target/ARM | |
| parent | 224180e81b34c99d15e35a4d4de6729357c6d372 (diff) | |
The different flavors of ARM have different valid subsets of registers. Check
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142706 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 7df743b750..72ea6ace52 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -6015,9 +6015,19 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { MachineInstrBuilder MIB(&*II); for (unsigned i = 0; SavedRegs[i] != 0; ++i) { - if (!TRC->contains(SavedRegs[i])) continue; - if (!DefRegs[SavedRegs[i]]) - MIB.addReg(SavedRegs[i], RegState::ImplicitDefine | RegState::Dead); + unsigned Reg = SavedRegs[i]; + if (Subtarget->isThumb2() && + !ARM::tGPRRegisterClass->contains(Reg) && + !ARM::hGPRRegisterClass->contains(Reg)) + continue; + else if (Subtarget->isThumb1Only() && + !ARM::tGPRRegisterClass->contains(Reg)) + continue; + else if (!Subtarget->isThumb() && + !ARM::GPRRegisterClass->contains(Reg)) + continue; + if (!DefRegs[Reg]) + MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); } break; |