diff options
| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
| commit | 5c062ad92672f22e61a4b20a9954af3db3b72bd6 (patch) | |
| tree | f65d4278663391396a3ae5ab55a3a4b7021200ed /lib/Target/ARM | |
| parent | 8da7a4668f6f32e565d426b5cca93eea9278f482 (diff) | |
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 10 |
2 files changed, 10 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3b647cdee2..a594271c94 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4128,8 +4128,8 @@ multiclass AsI1_bincc_irs<bits<4> opcod, string opc, let Inst{3-0} = shift{3-0}; } - def rsr : AsI1<opcod, (outs GPR:$Rd), - (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, + def rsr : AsI1<opcod, (outs GPRnopc:$Rd), + (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, opc, "\t$Rd, $Rn, $shift", []>, RegConstraint<"$Rn = $Rd"> { bits<4> Rd; diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 86f4d7b676..e52e6c7f07 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -869,8 +869,14 @@ static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo == 15) return MCDisassembler::Fail; - return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); + DecodeStatus S = MCDisassembler::Success; + + if (RegNo == 15) + S = MCDisassembler::SoftFail; + + Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + + return S; } static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, |