diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2011-06-27 21:26:13 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-27 21:26:13 +0000 |
| commit | 15993f83a419950f06d2879d6701530ae6449317 (patch) | |
| tree | 749e4564ae6f9d1f7c3539ccec1dfd88e1642bc9 /lib/Target/ARM | |
| parent | bea6f615eefae279e53bbb63a31d2c3c67274c45 (diff) | |
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/MLxExpansionPass.cpp | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 92c98da695..b76547653e 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1112,7 +1112,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB, const TargetInstrDesc &TID = TII.get(ADDriOpc); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); - MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this)); + MRI.constrainRegClass(BaseReg, TII.getRegClass(TID, 0, this)); MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg) .addFrameIndex(FrameIdx).addImm(Offset); diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index f4645f15a6..e4ec681d94 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1673,7 +1673,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, Ops.pop_back(); const TargetInstrDesc &TID = TII->get(NewOpc); - const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI); + const TargetRegisterClass *TRC = TII->getRegClass(TID, 0, TRI); MRI->constrainRegClass(EvenReg, TRC); MRI->constrainRegClass(OddReg, TRC); diff --git a/lib/Target/ARM/MLxExpansionPass.cpp b/lib/Target/ARM/MLxExpansionPass.cpp index f6d024232e..fc22861476 100644 --- a/lib/Target/ARM/MLxExpansionPass.cpp +++ b/lib/Target/ARM/MLxExpansionPass.cpp @@ -220,7 +220,7 @@ MLxExpansion::ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI, const TargetInstrDesc &TID1 = TII->get(MulOpc); const TargetInstrDesc &TID2 = TII->get(AddSubOpc); - unsigned TmpReg = MRI->createVirtualRegister(TID1.getRegClass(0, TRI)); + unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(TID1, 0, TRI)); MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), TID1, TmpReg) .addReg(Src1Reg, getKillRegState(Src1Kill)) |