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authorJohnny Chen <johnny.chen@apple.com>2011-04-05 22:57:07 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-04-05 22:57:07 +0000
commitc3281c10c94185e18338764b225a730a7c3e3ec4 (patch)
treed2501307a259747e16299c200c92fa38cd648f46 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
parentda19475328ece3da19437a2e9eef035dcafa2814 (diff)
A7.3 register encoding
Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index db76c11b7b..58f9c1f759 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -94,6 +94,16 @@ getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
}
// See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
+ // A7.3 register encoding
+ // Qd -> bit[12] == 0
+ // Qn -> bit[16] == 0
+ // Qm -> bit[0] == 0
+ //
+ // If one of these bits is 1, the instruction is UNDEFINED.
+ if (RegClassID == ARM::QPRRegClassID && slice(RawRegister, 0, 0) == 1) {
+ B->SetErr(-1);
+ return 0;
+ }
unsigned RegNum =
RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;