diff options
| author | Bill Wendling <isanbard@gmail.com> | 2010-11-30 00:48:15 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-11-30 00:48:15 +0000 |
| commit | 6e46d84eea97792a66c0bb64f26aad3976a23365 (patch) | |
| tree | 78d1f85ca257466ff7142e6c26d86a64b04cad28 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | |
| parent | 13815d9d3eec3d0ef2fc2f8a09e8ca8a9fa2654a (diff) | |
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index f73f6faaf9..752e2855dc 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -790,7 +790,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // Misc. Branch Instructions. // BLXr9, BXr9 -// BRIND, BX_RET +// BX, BX_RET static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { @@ -805,8 +805,8 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, if (Opcode == ARM::BX_RET) return true; - // BLXr9 and BRIND take one GPR reg. - if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) { + // BLXr9 and BX take one GPR reg. + if (Opcode == ARM::BLXr9 || Opcode == ARM::BX) { assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && "Reg operand expected"); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, |