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authorOwen Anderson <resistor@mac.com>2011-07-15 18:46:47 +0000
committerOwen Anderson <resistor@mac.com>2011-07-15 18:46:47 +0000
commit43967a97cf9a296623e1cf5ed643e2f40b7e5766 (patch)
tree7b6737998f0d7d67cd2e514e922d88cd7aed2425 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
parent739b65bf85cf7221b8a615e83dee11ec729e2649 (diff)
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp5
1 files changed, 0 insertions, 5 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 325a3ed2ad..d89c80a9d4 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -3093,11 +3093,6 @@ static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
: decodeNEONRm(insn))));
++OpIdx;
- // Special case handling for VMOVDneon and VMOVQ because they are marked as
- // N3RegFrm.
- if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
- return true;
-
// Dm = Inst{5:3-0} => NEON Rm
// or
// Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise