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authorJim Grosbach <grosbach@apple.com>2011-08-05 16:11:38 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-05 16:11:38 +0000
commit16578b50889329eb62774148091ba0f38b681a09 (patch)
tree2d49e839366f9b1dd768d26ebe7827d10cd98963 /lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
parentca8c70b9536bf351ee92395dae6f99a59c011a3d (diff)
ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp10
1 files changed, 8 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 26716763cf..d460ecd694 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1543,10 +1543,16 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
++OpIdx;
} else {
// Disassemble the offset reg (Rm).
- unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
- MI.addOperand(MCOperand::CreateImm(Offset));
+ // FIXME: Remove the 'else' once done w/ addrmode3 refactor.
+ if (Opcode == ARM::STRHTr || Opcode == ARM::LDRSBTr ||
+ Opcode == ARM::LDRHTr || Opcode == ARM::LDRSHTr)
+ MI.addOperand(MCOperand::CreateImm(getUBit(insn)));
+ else {
+ unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
+ MI.addOperand(MCOperand::CreateImm(Offset));
+ }
OpIdx += 2;
}