diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-15 20:51:32 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-15 20:51:32 +0000 |
| commit | c537f3be0c4ff7030afcdcd9f55133ce68eef773 (patch) | |
| tree | 1ef260b70c23da2da17566f030af288f86fa6963 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | f000957aadaf1f273c97b1b9d4e4c6f26608c435 (diff) | |
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index e7b555a22f..852c52af8b 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1094,6 +1094,21 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, unsigned P = fieldFromInstruction32(Insn, 24, 1); bool writeback = (W == 1) | (P == 0); + + // For {LD,ST}RD, Rt must be even, else undefined. + switch (Inst.getOpcode()) { + case ARM::STRD: + case ARM::STRD_PRE: + case ARM::STRD_POST: + case ARM::LDRD: + case ARM::LDRD_PRE: + case ARM::LDRD_POST: + if (Rt & 0x1) return false; + break; + default: + break; + } + if (writeback) { // Writeback if (P) U |= ARMII::IndexModePre << 9; |