diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-26 18:09:22 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-26 18:09:22 +0000 |
| commit | 96425c846494c1c20a4c931f4783571295ab170c (patch) | |
| tree | 2ba21db1832cba6964d0248c0ba0f30cd065efca /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 06a531ff63ff0eef8ac8fab38d148a968154c006 (diff) | |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index f1c5ce8bc5..3fd06a998b 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2310,12 +2310,15 @@ static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); - if (Inst.getOpcode() == ARM::tADR) - Inst.addOperand(MCOperand::CreateReg(ARM::PC)); - else if (Inst.getOpcode() == ARM::tADDrSPi) - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - else - return Fail; + switch(Inst.getOpcode()) { + case ARM::tADR: + break; + case ARM::tADDrSPi: + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); + break; + default: + return Fail; + } Inst.addOperand(MCOperand::CreateImm(imm)); return S; |