diff options
| author | Owen Anderson <resistor@mac.com> | 2011-09-23 21:07:25 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-09-23 21:07:25 +0000 |
| commit | 31d485ec9a2afcf83c5354061568b4280d61b574 (patch) | |
| tree | 0843fe3196bfb6bfdcfdde8b984edef4336f61fd /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | df0caeb6eca5c3424b4ccef5f489708392450982 (diff) | |
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 6be49169b4..a775cf61b5 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2660,7 +2660,7 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, break; default: { unsigned Rt = fieldFromInstruction32(Insn, 12, 4); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; } } |