diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-11 18:55:42 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-11 18:55:42 +0000 |
| commit | 2b7b238e843cbbe0682a3cc001fe514f4270a984 (patch) | |
| tree | 35b6b123313761ae61be25cfc4937af4fc41acfd /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 3dac0bec7e7874ffb378385b6160bd2117184ca9 (diff) | |
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 8c0faa895a..8a85cfade1 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -979,7 +979,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, idx_mode = ARMII::IndexModePost; if (reg) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; ARM_AM::ShiftOpc Opc = ARM_AM::lsl; switch( fieldFromInstruction32(Insn, 5, 2)) { case 0: |