diff options
| author | Owen Anderson <resistor@mac.com> | 2011-09-23 21:00:32 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-09-23 21:00:32 +0000 |
| commit | d2560565810d40afea87f2dfbe51e125d0dc80ab (patch) | |
| tree | 77f79d552049f9324223e32a866d50f1dde7f9be /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | b3e3b006bd5c82516d6fdb487d5c1263a5249474 (diff) | |
Thumb2 register-shifted-register loads cannot target the PC or the SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 6be49169b4..a775cf61b5 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2660,7 +2660,7 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, break; default: { unsigned Rt = fieldFromInstruction32(Insn, 12, 4); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; } } |