diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-09 23:25:42 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-09 23:25:42 +0000 |
| commit | c36481c4744cdbddec91dc3eca9245acaf2982da (patch) | |
| tree | 4e8237c6452c0a70960390a875083ea3835f88eb /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 77c714027ce4188be0af75b05cbbd493221fc22f (diff) | |
Tighten operand checking on memory barrier instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index a3fa138ba6..4e7e582c61 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -131,6 +131,8 @@ static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, @@ -2268,8 +2270,7 @@ static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, } unsigned imm = fieldFromInstruction32(Insn, 0, 4); - Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return DecodeMemBarrierOption(Inst, imm, Address, Decoder); } unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; @@ -2347,3 +2348,24 @@ static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, return true; } + +static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + switch (Val) { + default: + return false; + case 0xF: // SY + case 0xE: // ST + case 0xB: // ISH + case 0xA: // ISHST + case 0x7: // NSH + case 0x6: // NSHST + case 0x3: // OSH + case 0x2: // OSHST + break; + } + + Inst.addOperand(MCOperand::CreateImm(Val)); + return true; +} + |