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authorOwen Anderson <resistor@mac.com>2011-08-22 17:56:58 +0000
committerOwen Anderson <resistor@mac.com>2011-08-22 17:56:58 +0000
commitb113ec55e897c85fda606409c1eedec4f89ec53f (patch)
tree90208d469d2de79dbdb8baac226d270e21ee45dd /lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parent011af5ca801cb95117a9abe2b217f78e2a7c8899 (diff)
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassembler.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index a57102c6e1..ebcb798969 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2322,7 +2322,7 @@ static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateImm(Val << 2));
+ Inst.addOperand(MCOperand::CreateImm(Val));
return Success;
}