diff options
| author | Owen Anderson <resistor@mac.com> | 2011-07-21 23:38:37 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-07-21 23:38:37 +0000 |
| commit | 152d4a4bb6b75de740b4b8a9f48abb9069d50c17 (patch) | |
| tree | 75a3b965a0f354f467e1d6e4b4930deaad0530e8 /lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 856e13ddace4174ad1b07f65ebb18b2fd835ed57 (diff) | |
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 827ad0fb9f..fd8f815207 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -626,13 +626,9 @@ public: } void addShiftedImmOperands(MCInst &Inst, unsigned N) const { - assert(N == 3 && "Invalid number of operands!"); + assert(N == 2 && "Invalid number of operands!"); assert(isShiftedImm() && "addShiftedImmOperands() on non ShiftedImm!"); Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg)); - if (ShiftedImm.ShiftTy == ARM_AM::rrx) - Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg)); - else - Inst.addOperand(MCOperand::CreateReg(0)); Inst.addOperand(MCOperand::CreateImm( ARM_AM::getSORegOpc(ShiftedImm.ShiftTy, ShiftedImm.ShiftImm))); } |