Insert denominator zero checks for NaCl

This IR pass for ARM inserts a comparison and a branch to trap if the
denominator of a DIV or REM instruction is zero.  This makes ARM fault
identically to x86 in this case.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=2833
R=eliben@chromium.org

Review URL: https://codereview.chromium.org/14607004

1 files changed, 15 insertions, 0 deletions

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index c02e981e54..499f974b96 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -20,6 +20,9 @@
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
+// @LOCALMOD-START
+#include "llvm/Transforms/NaCl.h"
+// @LOCALMOD-END
 #include "llvm/Transforms/Scalar.h"
 using namespace llvm;
 
@@ -141,6 +144,9 @@ public:
   virtual bool addPreRegAlloc();
   virtual bool addPreSched2();
   virtual bool addPreEmitPass();
+// @LOCALMOD-START
+  virtual void addIRPasses();
+// @LOCALMOD-END
 };
 } // namespace
 
@@ -229,6 +235,15 @@ bool ARMPassConfig::addPreEmitPass() {
   return true;
 }
 
+// @LOCALMOD-START
+void ARMPassConfig::addIRPasses() {
+  if (getARMSubtarget().isTargetNaCl()) {
+    addPass(createInsertDivideCheckPass());
+  }
+  TargetPassConfig::addIRPasses();
+}
+// @LOCALMOD-END
+
 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
                                           JITCodeEmitter &JCE) {
   // Machine code emitter pass for ARM.