diff options
| author | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:40 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:40 +0000 |
| commit | fc992996f751e0941951b6d08d8f1e80ebec1385 (patch) | |
| tree | 9205e39624f5c786dee5160b882d65c7865e45b2 /lib/Target/ARM/ARMSubtarget.cpp | |
| parent | 4eb4e5eb224b3d737558bcda8a0a369cc9d800e6 (diff) | |
misched: Added MultiIssueItineraries.
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index ac568b1a08..0bea9e4b2b 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -200,13 +200,14 @@ void ARMSubtarget::computeIssueWidth() { const InstrStage *IS = InstrItins.Stages + itin->FirstStage; allStage1Units |= IS->getUnits(); } - InstrItins.IssueWidth = 0; + InstrItins.Props.IssueWidth = 0; while (allStage1Units) { - ++InstrItins.IssueWidth; + ++InstrItins.Props.IssueWidth; // clear the lowest bit allStage1Units ^= allStage1Units & ~(allStage1Units - 1); } - assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); + assert(InstrItins.Props.IssueWidth <= 2 && + "itinerary bug, too many stage 1 units"); } bool ARMSubtarget::enablePostRAScheduler( |