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| author | James Molloy <james.molloy@arm.com> | 2011-09-28 14:21:38 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2011-09-28 14:21:38 +0000 |
| commit | acad68da50581de905a994ed3c6b9c197bcea687 (patch) | |
| tree | 762c6b5dbdef98ff11c9c44d6bdffcdc6535e4f2 /lib/Target/ARM/ARMSubtarget.cpp | |
| parent | 113aa8612010434069fc5b5e09f6b2667e03e173 (diff) | |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index f01d1d41cf..82e542281e 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -55,6 +55,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, , InThumbMode(false) , InNaClMode(false) , HasThumb2(false) + , IsMClass(false) , NoARM(false) , PostRAScheduler(false) , IsR9Reserved(ReserveR9) |