diff options
| author | David Sehr <sehr@chromium.org> | 2012-10-30 17:33:49 -0700 |
|---|---|---|
| committer | David Sehr <sehr@chromium.org> | 2012-10-30 17:33:49 -0700 |
| commit | 5aad254469ae849ba380eaa46a7d2142ba234f6e (patch) | |
| tree | 51681f689f3780206602909ce7233247d2584045 /lib/Target/ARM/ARMSubtarget.cpp | |
| parent | e522cf99cb4da5dcf110efe920d885c084ff6f3f (diff) | |
Align ARM stack 0mod16.
Includes change to add some asserts to legalizing addresses for NaCl.
BUG= http://code.google.com/p/nativeclient/issues/detail?id=3116
TEST=none
Review URL: https://codereview.chromium.org/11285009
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 6562600202..d2f0a28f78 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -137,6 +137,12 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, } // @LOCALMOD-BEGIN + // Advanced SIMD and Q registers are part of the NaCl ARM ABI. The ARM + // EABI specifies only an 8 byte alignment, which can result in poor + // performance for these 16 byte data types if they straddle cache lines, etc. + // Therefore, NaCl aligns stack frames 0mod16. + if (isTargetNaCl()) + stackAlignment = 16; // NaCl uses MovT to avoid generating constant islands. if (isTargetNaCl() && !useConstPool()) UseMovt = true; |