diff options
| author | Dan Gohman <gohman@apple.com> | 2008-12-03 02:30:17 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-12-03 02:30:17 +0000 |
| commit | 41474baac839da410302950305722cb0e026a094 (patch) | |
| tree | d36d696d3d8328b7c3db385d50c50f0ef584359f /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | c70f3295438488e1e34eb212d1f8ec55bbf43935 (diff) | |
Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index b85daa13f5..cd5f321f98 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -834,7 +834,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, assert(Offset && "This code isn't needed if offset already handled!"); if (isThumb) { - if (Desc.isSimpleLoad()) { + if (Desc.mayLoad()) { // Use the destination register to materialize sp + offset. unsigned TmpReg = MI.getOperand(0).getReg(); bool UseRR = false; |