diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-06-04 01:23:30 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-06-04 01:23:30 +0000 |
| commit | 958e4e1967838766d327f1112e5b4900be939275 (patch) | |
| tree | 6c0e4dae0e91e71d02eef71031e6cd5cf0847e1a /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | f62546ab046d4bc2f055921f25f127fbb942b806 (diff) | |
more dbg_value adjustments so debug info doesn't affect codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 955ab3f7e2..b082295270 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1291,7 +1291,7 @@ static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, // some day. SmallSet<unsigned, 4> AddedRegPressure; while (++I != E) { - if (MemOps.count(&*I)) + if (I->isDebugValue() || MemOps.count(&*I)) continue; const TargetInstrDesc &TID = I->getDesc(); if (TID.isCall() || TID.isTerminator() || TID.hasUnmodeledSideEffects()) @@ -1574,7 +1574,9 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) { break; } - MI2LocMap[MI] = Loc++; + if (!MI->isDebugValue()) + MI2LocMap[MI] = ++Loc; + if (!isMemoryOp(MI)) continue; unsigned PredReg = 0; |